@@ -166,22 +166,40 @@ zephyr_udc0: &usbd {
166166 lsb-microamp = <100>;
167167 label = "INA219";
168168 };
169- mcp23017: mcp23017@20 {
170- compatible = "microchip,mcp23017";
171- reg = <0x20>;
172- gpio-controller;
173- #gpio-cells = <2>;
174-
175- // GPIO line names for traceability
176- gpio-line-names = "FACE4_ENABLE", "FACE0_ENABLE", "FACE1_ENABLE", "FACE2_ENABLE",
177- "FACE3_ENABLE", "FACE5_ENABLE", "READONLY", "CHARGE",
178- "ENABLE_Heater", "PAYLOAD_PWR_ENABLE", "FIRE_DEPLOY2_B", "PAYLOAD_BATT_ENABLE",
179- "RF2_IO2", "RF2_IO1", "RF2_IO0", "RF2_IO3";
180-
181- reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
182-
183- ngpios = <16>;
184- };
169+ mcp23017: mcp23017@20 {
170+ compatible = "microchip,mcp23017";
171+ reg = <0x20>;
172+ gpio-controller;
173+ #gpio-cells = <2>;
174+
175+ /* gpio-line-names must match the numeric indexes used below. The
176+ * topology and gpio nodes expect the following mapping (index : name):
177+ * 0: ENABLE_HEATER (GPA0)
178+ * 1: PAYLOAD_PWR_ENABLE (GPA1)
179+ * 2: FIRE_DEPLOY2_B (GPA2)
180+ * 3: PAYLOAD_BATT_ENABLE (GPA3)
181+ * 4: RF2_IO2 (GPA4)
182+ * 5: RF2_IO1 (GPA5)
183+ * 6: RF2_IO0 (GPA6)
184+ * 7: RF2_IO3 (GPA7)
185+ * 8: FACE4_ENABLE (GPB0)
186+ * 9: FACE0_ENABLE (GPB1)
187+ * 10: FACE1_ENABLE (GPB2)
188+ * 11: FACE2_ENABLE (GPB3)
189+ * 12: FACE3_ENABLE (GPB4)
190+ * 13: FACE5_ENABLE (GPB5)
191+ * 14: READONLY (GPB6)
192+ * 15: CHARGE (GPB7)
193+ */
194+ gpio-line-names = "ENABLE_HEATER", "PAYLOAD_PWR_ENABLE", "FIRE_DEPLOY2_B", "PAYLOAD_BATT_ENABLE",
195+ "RF2_IO2", "RF2_IO1", "RF2_IO0", "RF2_IO3",
196+ "FACE4_ENABLE", "FACE0_ENABLE", "FACE1_ENABLE", "FACE2_ENABLE",
197+ "FACE3_ENABLE", "FACE5_ENABLE", "READONLY", "CHARGE";
198+
199+ reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
200+
201+ ngpios = <16>;
202+ };
185203};
186204
187205// GPIO Expander IO
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