Remove slow-clocks from default features in toml file as well as improperly hard-coded clock reg values

Remove some hardcoded clock reg settings and use the config blob fields instead. Remove slow-clocks feature from default as clock config passed into init function should be fully utilized now. Pending full removal of slow-clocks feature after more thorough validation

Add default impl for ClockConfig

Author: madeleyneVaca

Cargo.toml

@@ -21,7 +21,7 @@ flavors = [
 features = ["time", "defmt", "unstable-pac", "time-driver-os-timer"]
 
 [features]
-default = ["rt", "time", "slow-clocks"]
+default = ["rt", "time"]
 
 ## Cortex-M runtime (enabled by default)
 rt = ["mimxrt685s-pac?/rt", "mimxrt633s-pac?/rt"]

src/clocks.rs

@@ -143,6 +143,12 @@ impl ClockConfig {
     }
 }
 
+impl Default for ClockConfig {
+    fn default() -> Self {
+        Self::crystal()
+    }
+}
+
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// Clock state enum
@@ -711,7 +717,7 @@ impl MultiSourceClock for MainPllClkConfig {
 
 impl ConfigurableClock for MainPllClkConfig {
     fn enable_and_reset(&self) -> Result<(), ClockError> {
-        MainPllClkConfig::init_syspll();
+        MainPllClkConfig::init_syspll(&self);
 
         MainPllClkConfig::init_syspll_pfd0(self.pfd0);
 
@@ -874,7 +880,7 @@ impl MainPllClkConfig {
         }
     }
 
-    pub(self) fn init_syspll() {
+    pub(self) fn init_syspll(&self) {
         // SAFETY: unsafe needed to take pointers to Sysctl0 and Clkctl0
         let clkctl0 = unsafe { crate::pac::Clkctl0::steal() };
         let sysctl0 = unsafe { crate::pac::Sysctl0::steal() };
@@ -884,20 +890,35 @@ impl MainPllClkConfig {
             .pdruncfg0_set()
             .write(|w| w.syspllldo_pd().set_pdruncfg0().syspllana_pd().set_pdruncfg0());
 
-        #[cfg(not(feature = "slow-clocks"))]
-        clkctl0.syspll0clksel().write(|w| w.sel().ffro_div_2());
-        #[cfg(feature = "slow-clocks")]
-        clkctl0.syspll0clksel().write(|w| w.sel().sfro_clk());
+        match self.src {
+            MainPllClkSrc::ClkIn => {
+                clkctl0.syspll0clksel().write(|w| w.sel().sysxtal_clk());
+            }
+            MainPllClkSrc::FFRO => {
+                // FFRO Clock is divided by 2
+                clkctl0.syspll0clksel().write(|w| w.sel().ffro_div_2());
+            }
+            MainPllClkSrc::SFRO => {
+                clkctl0.syspll0clksel().write(|w| w.sel().sfro_clk());
+            }
+        }
+
         // SAFETY: unsafe needed to write the bits for both num and denom
         clkctl0.syspll0num().write(|w| unsafe { w.num().bits(0x0) });
         clkctl0.syspll0denom().write(|w| unsafe { w.denom().bits(0x1) });
 
-        // kCLOCK_SysPllMult22
-        // really should be using the mult defined in main pll config
-        #[cfg(feature = "slow-clocks")]
-        clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_16());
-        #[cfg(not(feature = "slow-clocks"))]
-        clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_22());
+        // kCLOCK_SetSysPll<Mult>
+        // Use the mult defined in main pll config
+        // if invalid, use 22 as default instead of panicking
+        match self.mult.load(Ordering::Relaxed) {
+            16 => clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_16()),
+            17 => clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_17()),
+            20 => clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_20()),
+            22 => clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_22()),
+            27 => clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_27()),
+            33 => clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_33()),
+            _ => clkctl0.syspll0ctl0().modify(|_, w| w.mult().div_22()),
+        };
 
         // Clear System PLL reset
         clkctl0.syspll0ctl0().modify(|_, w| w.reset().normal());
@@ -1548,11 +1569,10 @@ fn init_clock_hw(config: ClockConfig) -> Result<(), ClockError> {
 
     config.main_pll_clk.enable_and_reset()?;
 
-    #[cfg(feature = "slow-clocks")]
     fsl_power::set_ldo_voltage_for_freq(
         fsl_power::TempRange::TempN20CtoP85C,
         fsl_power::VoltOpRange::Low,
-        140_000_000,
+        config.main_clk.freq.load(Ordering::Relaxed),
         0,
     );