Commit b5f7c51
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uart: fix polling edge case in buffered read (#548)
This pull request makes a targeted adjustment to the `UartRx`
asynchronous receive logic to more accurately determine the amount of
available data in the buffer, particularly when handling a DMA transfer
completion edge case.
- **Buffer availability calculation fix:**
* The logic for when `xfercount == 0x3FF` has been updated so that
instead of skipping the case with `continue`, it now sets `available =
0`, ensuring that the available data is correctly reported as zero when
the transfer has just finished. This prevents potential calculation
errors in the number of bytes available to read.1 parent 8ad0644 commit b5f7c51
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