Add Novatek chipid via pinmux value

Author: dimerr

src/chipid.c

@@ -46,7 +46,7 @@ static const manufacturers_t manufacturers[] = {
 #ifdef __arm__
     {"SStar", sstar_detect_cpu, VENDOR_SSTAR, sstar_setup_hal},
     {"MStar", mstar_detect_cpu, NULL, sstar_setup_hal},
-    {"Novatek", novatek_detect_cpu, NULL, novatek_setup_hal},
+    {"Novatek", novatek_detect_cpu, VENDOR_NOVATEK, novatek_setup_hal},
     {"Grain", gm_detect_cpu, VENDOR_GM, gm_setup_hal},
     {"FH", fh_detect_cpu, VENDOR_FH, fh_setup_hal},
     {NULL /* Generic */, rockchip_detect_cpu, VENDOR_ROCKCHIP, rockchip_setup_hal},
@@ -55,6 +55,7 @@ static const manufacturers_t manufacturers[] = {
     {NULL, allwinner_detect_cpu, VENDOR_ALLWINNER, allwinner_setup_hal}
 #endif
 #if defined(__aarch64__) || defined(_M_ARM64)
+    {NULL, novatek_detect_cpu, VENDOR_NOVATEK, novatek_setup_hal},
     {NULL, tegra_detect_cpu, "Nvidia", tegra_setup_hal},
 #endif
 };

src/chipid.h

@@ -10,6 +10,7 @@
 #define VENDOR_GOKE "Goke"
 #define VENDOR_HISI "HiSilicon"
 #define VENDOR_INGENIC "Ingenic"
+#define VENDOR_NOVATEK "Novatek"
 #define VENDOR_ROCKCHIP "Rockchip"
 #define VENDOR_SSTAR "SigmaStar"
 

src/hal/novatek.c

@@ -9,8 +9,6 @@
 #include "hal/common.h"
 #include "tools.h"
 
-// TODO: /proc/nvt_info/nvt_pinmux/chip_id
-
 static unsigned char sony_addrs[] = {0x34, 0};
 static unsigned char ssens_addrs[] = {0x60, 0};
 static unsigned char omni_addrs[] = {0x6c, 0};
@@ -24,14 +22,49 @@ static sensor_addr_t novatek_possible_i2c_addrs[] = {
     {SENSOR_GALAXYCORE, gc_addrs}, {SENSOR_TECHPOINT, tp_addrs},
     {0, NULL}};
 
+static bool nvt_get_chip_id() {
+    uint16_t reg;
+    unsigned int chip_id = 0;
+    char buf[8];
+    char *endptr;
+
+    if (line_from_file("/proc/nvt_info/nvt_pinmux/chip_id", "(.+)", buf,
+                       sizeof(buf))) {
+
+        reg = (uint16_t)strtol(buf, &endptr, 16);
+        switch (reg) {
+        case 0x5021:
+            strcpy(chip_name, "NT98562");
+            return true;
+        case 0x7021:
+            strcpy(chip_name, "NT98566");
+            return true;
+        case 0x8B20:
+            strcpy(chip_name, "NT98332G");
+            return true;
+        }
+    }
+
+    // if (mem_reg(IOADDR_TOP_REG_BASE + TOP_VERSION_REG_OFS, (uint32_t *)&reg,
+    //             OP_READ)) {
+    //     chip_id = (reg >> 16) & 0xFFFF;
+    // }
+    // printf("reg %x\n", chip_id);
+    return false;
+}
+
 bool novatek_detect_cpu(char *chip_name) {
     char buf[256];
 
+    if(nvt_get_chip_id())
+        return true;
+
     if (!line_from_file("/proc/device-tree/model", "Novatek ([A-Z]+[0-9]+)",
                         buf, sizeof(buf)))
         return false;
 
     strcpy(chip_name, buf);
+
     return true;
 }
 
@@ -82,36 +115,3 @@ void novatek_setup_hal() {
     hal_totalmem = novatek_totalmem;
 #endif
 }
-
-enum CHIP_ID {
-    CHIP_NA51055 = 0x4821, // NT98525, 128Kb L2, 5M@30
-                           // NT98528, 256Kb L2, 4K@30
-    CHIP_NA51084 = 0x5021,
-    CHIP_NA51089 = 0x7021, // NT98562, 64Mb internal RAM
-                           // NT98566, 128Mb internal RAM
-    CHIP_NA51090 = 0xBC21
-};
-
-#define TOP_VERSION_REG_OFS 0xF0
-
-/* na51000, na51089, na51068, na51000, na51090, na51055 */
-#define IOADDR_GLOBAL_BASE (0xF0000000)
-/* na51090 */
-//#define IOADDR_GLOBAL_BASE (0x2F0000000)
-
-/* na51000, na51089, na51000, na51090, na51090, na51055 */
-#define IOADDR_TOP_REG_BASE (IOADDR_GLOBAL_BASE + 0x00010000)
-/* na51068 */
-//#define IOADDR_TOP_REG_BASE (IOADDR_GLOBAL_BASE + 0x0E030000)
-
-static uint32_t nvt_get_chip_id() {
-    uint32_t reg;
-    unsigned int chip_id = 0;
-
-    if (mem_reg(IOADDR_TOP_REG_BASE + TOP_VERSION_REG_OFS, (uint32_t *)&reg,
-                OP_READ)) {
-        chip_id = (reg >> 16) & 0xFFFF;
-    }
-
-    return chip_id;
-}

src/hal/novatek.h

@@ -7,4 +7,26 @@ bool novatek_detect_cpu(char *chip_name);
 unsigned long novatek_totalmem(unsigned long *media_mem);
 void novatek_setup_hal();
 
+#define TOP_VERSION_REG_OFS 0xF0
+
+/* na51000, na51089, na51068, na51000, na51090, na51055 */
+#define IOADDR_GLOBAL_BASE (0xF0000000)
+/* na51090 */
+//#define IOADDR_GLOBAL_BASE (0x2F0000000)
+
+/* na51000, na51089, na51000, na51090, na51090, na51055 */
+#define IOADDR_TOP_REG_BASE (IOADDR_GLOBAL_BASE + 0x00010000)
+/* na51068 */
+//#define IOADDR_TOP_REG_BASE (IOADDR_GLOBAL_BASE + 0x0E030000)
+
+enum CHIP_ID {
+    CHIP_NA51055 = 0x4821, // NT98525, 128Kb L2, 5M@30
+                           // NT98528, 256Kb L2, 4K@30
+    CHIP_NA51084 = 0x5021,
+    CHIP_NA51089 = 0x7021, // NT98562, 64Mb internal RAM
+                           // NT98566, 128Mb internal RAM
+    CHIP_NA51090 = 0xBC21,
+    CHIP_NA51103 = 0x8B20 // NVT98332G
+};
+
 #endif /* HAL_NOVATEK_H */