RISC-V - Register spillage in GEMV due to manual 4-way unrolling and use of LMUL > 2

[ChipKerchner]

Performance is being compromised in RISC-V GEMV due to manual 4-way unrolling and use of LMUL > 2. Using these 2 conditions together can cause vector registers to be spilled. The inner loops of gemv_n_vector and gemv_t_vector should be reworked to avoid this.

FYI - there are only 32 vector registers. LMUL = 8 uses 8 vector registers per variable.

Testing should be done with RVV 1.0 for RISCV64_ZVL128B and RISCV64_ZVL256B.

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[ChipKerchner]

The best performance I've found so far is removing the manual unrolling in gemv_t_vector.c.
The best performance I've found so far is reducing the manual unrolling to 2-way (or none) in gemv_n_vector.c (6.5% better than 4-way).

Replacing with gemm_t_rvv.c and gemm_n_rvv.c has noticeably better performance (10%)