I2S0 can't output mclk

[lihing1994]

I'm working on integrating the NXP SGTL5000 codec with the MA35D1 platform. The SGTL5000 is configured as a slave device on both the I2S0 and I2C1 buses. However, the codec is not detected by the i2cdetect tool, while all other devices on the same I2C bus are detected correctly. Based on my understanding, if i2cdetect fails to detect the SGTL5000, it likely indicates that the chip isn't hardware-ready for communication.

According to the SGTL5000 datasheet: "The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK cycles after all power rails have been brought up. After this time, communication can start.". This implies that a stable SYS_MCLK must be present before any I2C communication can succeed. I probed the I2S0_MCLK pin and observed a frequency significantly below the expected 12.288 MHz—less than 10 Hz, in fact. In my device tree (which inherits from ma35d1.dtsi), I have configured the relevant child nodes for I2S0 and clock generation as described in the MA35D1 Linux User Manual. Despite this, the correct MCLK is not generated. Following are the related part of the device tree

&i2s0{
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2s0>;
        mclk_out = <12288000>;
};

&clk{
        assigned-clock-rates =<1000000000>,
                                <266000000>, <196608000>,
                                <500000000>, <102000000>;
};

&pinctrl
     i2s0 {
                pinctrl_i2s0: i2s0grp{
                        nuvoton,pins =
                                <SYS_GPG_MFPH_PG11MFP_I2S0_MCLK         &pcfg_default>,
                                <SYS_GPG_MFPH_PG12MFP_I2S0_LRCK         &pcfg_default>,
                                <SYS_GPG_MFPH_PG13MFP_I2S0_BCLK         &pcfg_default>,
                                <SYS_GPG_MFPH_PG14MFP_I2S0_DI           &pcfg_default>,
                                <SYS_GPG_MFPH_PG15MFP_I2S0_DO           &pcfg_default>;
                };
        };
};

While reviewing the MA35D1 Technical Reference Manual (TRM), I noticed a key detail: "When the chip enters debug mode, this pin will be automatically forced to JTAG functionality by hardware, and other pinout functions of this pin will be disabled.". This raises the concern that the chip might be in debug mode, causing the I2S0_* pins—specifically I2S0_MCLK—to be repurposed for JTAG, which would suppress the expected clock output. Without a proper MCLK, the SGTL5000 remains in reset, and I2C communication fails.

Is there a way to confirm whether the MA35D1 is currently operating in debug mode? Are there any hardware registers, boot mode settings, or external indicators I can check to verify this?

Thanks a lot!

[lihing1994]

Here is the screenshot of I2S0 pin function section from MA35D1 Technical Reference Manual (TRM) .

[cwweng-nuvoton]

Which MA35D1 platform are you using ?
NuMaker-IoT_MA35D16F90 or NuMaker-HMI-MA35D1?

[cwweng-nuvoton]

For NuMaker-IoT_MA35D16F90,
PG11~15 are default for I2S0 interface. You can measure I2S0_MCLK on R145.

If you want to use JTAG interface for debugging, you have to modify the circuit by shorting R41~45.

[lihing1994]

Which MA35D1 platform are you using ?
NuMaker-IoT_MA35D16F90 or NuMaker-HMI-MA35D1?

I’m working on a customized SoM that uses Nuvoton’s SoC, the MA35D16F987C. Also, thanks for sharing the hardware schematic for I2S. I noticed that in Nuvoton’s design, there are series resistors (R145–R151) connected to pins PG11–PG15. However, in the customized SoM I’m working on, these resistors are not present.

Do you know if these resistors are required for the I2S bus to function correctly?

[cwweng-nuvoton]

The resistors are not required for I2S audio function.