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wmaroneAMDwmaroneAMD
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Updated tests for output
Made tests outputs more consistent, but further refinements are necessary. Also added a test end print and adjusted the script to key off of it.
1 parent 7f11e85 commit 14ad589

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9 files changed

+58
-55
lines changed

9 files changed

+58
-55
lines changed

‎scripts/uart-test-exec.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -317,7 +317,7 @@ def monitor_test_execution(self, timeout: int = 600) -> bool:
317317
test_results['skipped'] += 1
318318

319319
# Check for completion or failure
320-
if 'Test Suite' in line and 'Complete' in line:
320+
if 'COMPLETE' in line:
321321
self.log(f"\nTest execution completed!")
322322
self.log(f"Results: {test_results}")
323323
return test_results['failed'] == 0

‎src/main.rs‎

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -177,10 +177,10 @@ fn validate_digest(
177177
}
178178

179179
if matches && byte_index == expected.len() {
180-
writeln!(uart, "{algorithm} test vector validation: PASSED ✅").unwrap();
180+
writeln!(uart, "{algorithm} test vector validation: PASS").unwrap();
181181
true
182182
} else {
183-
writeln!(uart, "{algorithm} test vector validation: FAILED ❌").unwrap();
183+
writeln!(uart, "{algorithm} test vector validation: FAIL").unwrap();
184184
write!(uart, "Expected: ").unwrap();
185185
for &byte in expected {
186186
write!(uart, "{byte:02x}").unwrap();
@@ -226,9 +226,9 @@ fn test_owned_sha256(uart: &mut UartController<'_>, hace: ast1060_pac::Hace) {
226226
];
227227

228228
if validate_digest(&digest.value, &expected_sha256, "SHA256", uart) {
229-
writeln!(uart, "SHA256 owned API: PASSED ✅").unwrap();
229+
writeln!(uart, "SHA256 owned API: PASS").unwrap();
230230
} else {
231-
writeln!(uart, "SHA256 owned API: FAILED ❌").unwrap();
231+
writeln!(uart, "SHA256 owned API: FAIL").unwrap();
232232
}
233233
}
234234

@@ -254,17 +254,17 @@ fn test_owned_sha384(uart: &mut UartController<'_>, hace: ast1060_pac::Hace) {
254254
];
255255

256256
if validate_digest(&digest.value, &expected_sha384, "SHA384", uart) {
257-
writeln!(uart, "SHA384 owned API: PASSED ✅").unwrap();
257+
writeln!(uart, "SHA384 owned API: PASS").unwrap();
258258
} else {
259-
writeln!(uart, "SHA384 owned API: FAILED ❌").unwrap();
259+
writeln!(uart, "SHA384 owned API: FAIL").unwrap();
260260
}
261261

262262
// Demonstrate controller recovery by using it again
263263
let context2 = recovered_controller.init(Sha2_384).unwrap();
264264
let context2 = context2.update(b"Reused controller").unwrap();
265265
let (_digest2, _final_controller) = context2.finalize().unwrap();
266266

267-
writeln!(uart, "Controller recovery: PASSED ✅").unwrap();
267+
writeln!(uart, "Controller recovery: PASS").unwrap();
268268
}
269269

270270
/// Test owned SHA512 API demonstrating cancellation
@@ -278,7 +278,7 @@ fn test_owned_sha512(uart: &mut UartController<'_>, hace: ast1060_pac::Hace) {
278278
// Demonstrate cancellation - returns controller without computing digest
279279
let recovered_controller = context.cancel();
280280

281-
writeln!(uart, "SHA512 cancellation: PASSED ✅").unwrap();
281+
writeln!(uart, "SHA512 cancellation: PASS").unwrap();
282282

283283
// Use recovered controller for actual computation with known test vector
284284
// Test with known test vector: "abc" -> SHA512
@@ -300,9 +300,9 @@ fn test_owned_sha512(uart: &mut UartController<'_>, hace: ast1060_pac::Hace) {
300300
];
301301

302302
if validate_digest(&digest.value, &expected_sha512, "SHA512", uart) {
303-
writeln!(uart, "SHA512 owned API: PASSED ✅").unwrap();
303+
writeln!(uart, "SHA512 owned API: PASS").unwrap();
304304
} else {
305-
writeln!(uart, "SHA512 owned API: FAILED ❌").unwrap();
305+
writeln!(uart, "SHA512 owned API: FAIL").unwrap();
306306
}
307307
}
308308

@@ -372,6 +372,9 @@ fn main() -> ! {
372372
gpio_test::test_gpio_flash_power(&mut uart_controller);
373373
spi::spitest::test_spi2(&mut uart_controller);
374374
}
375+
376+
writeln!(uart_controller, "\r\nCOMPLETE\r\n").unwrap();
377+
375378
// Initialize the peripherals here if needed
376379
loop {
377380
cortex_m::asm::wfi();

‎src/spi/spitest.rs‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ pub fn test_read_jedec<D: SpiNorDevice<Error = E>, E>(uart: &mut UartController<
187187
astdebug::print_array_u8(uart, &id);
188188
}
189189
_ => {
190-
test_log!(uart, "Error:: Failed to read JEDEC ID");
190+
test_log!(uart, "Error:: Failed to read JEDEC ID (FAIL)");
191191
}
192192
}
193193
}
@@ -282,9 +282,9 @@ pub fn test_cs<D: SpiNorDevice<Error = E>, E>(
282282
== core::slice::from_raw_parts(ptr_read, len);
283283
}
284284
if result {
285-
test_log!(uart, "read write test passed!");
285+
test_log!(uart, "read write test PASS!");
286286
} else {
287-
test_log!(uart, "ERROR:: read write test failed!!");
287+
test_log!(uart, "ERROR:: read write test FAIL!!");
288288
test_log!(uart, "write buffer:");
289289
astdebug::print_array_u8(uart, wbuf);
290290
test_log!(uart, "read buffer:");
@@ -448,10 +448,10 @@ pub fn test_spi(uart: &mut UartController<'_>) {
448448
match flash_device.nor_read_jedec_id() {
449449
Ok(id) => match NorFlashBlockDevice::from_jedec_id(flash_device, id) {
450450
Ok(mut blockdev) => test_block_device::<_>(&mut blockdev),
451-
Err(_e) => test_log!(uart, "start block device using jedec id failed"),
451+
Err(_e) => test_log!(uart, "start block device using jedec id failed (FAIL)"),
452452
},
453453
_ => {
454-
test_log!(uart, "Error:: Failed to read JEDEC ID");
454+
test_log!(uart, "Error:: Failed to read JEDEC ID (FAIL)");
455455
}
456456
}
457457
} else {
@@ -591,8 +591,8 @@ pub fn test_block_device<T: SpiNorDevice>(blockdev: &mut NorFlashBlockDevice<T>)
591591
testsize
592592
);
593593
match blockdev.program(norflashblockdevice::BlockAddrUsize(addr), wbuf) {
594-
Ok(()) => test_log!(uartc, "program successful"),
595-
Err(_e) => test_log!(uartc, "program failed"),
594+
Ok(()) => test_log!(uartc, "program PASS"),
595+
Err(_e) => test_log!(uartc, "program FAIL"),
596596
}
597597

598598
let _ = blockdev.read(norflashblockdevice::BlockAddrUsize(addr), rbuf);
@@ -603,9 +603,9 @@ pub fn test_block_device<T: SpiNorDevice>(blockdev: &mut NorFlashBlockDevice<T>)
603603
== core::slice::from_raw_parts(ptr_read, testsize);
604604
}
605605
if result {
606-
test_log!(uartc, "read write test passed!");
606+
test_log!(uartc, "read write test passed (PASS)!");
607607
} else {
608-
test_log!(uartc, "ERROR:: read write test failed!!");
608+
test_log!(uartc, "ERROR:: read write test failed (FAIL)!!");
609609
test_log!(uartc, "write buffer:");
610610
astdebug::print_array_u8(&mut uartc, wbuf);
611611
test_log!(uartc, "read buffer:");

‎src/tests/functional/ecdsa_test.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -107,9 +107,9 @@ pub fn run_ecdsa_tests(
107107
writeln!(uart, "\r\nTest case {i}... ").unwrap();
108108

109109
let _ = match (result.is_ok(), vec.result) {
110-
(true, true) => writeln!(uart, "\rresult expected (pass), Pass"),
111-
(false, false) => writeln!(uart, "\rresult expected (fail), Pass"),
112-
_ => writeln!(uart, "\rresult unexpected (got {result:?}), Failed"),
110+
(true, true) => writeln!(uart, "\rresult expected (pass), PASS"),
111+
(false, false) => writeln!(uart, "\rresult expected (fail), PASS"),
112+
_ => writeln!(uart, "\rresult unexpected (got {result:?}), FAIL"),
113113
};
114114
}
115115
}

‎src/tests/functional/gpio_test.rs‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -34,24 +34,24 @@ pub fn test_gpioa(uart: &mut UartController<'_>) {
3434
let mut pa3 = gpioa.pa3.into_open_drain_output::<Floating>();
3535
pa3.set_low().unwrap();
3636
if pa3.is_set_low().unwrap() {
37-
uart.write_all(b"\rGPIOA pin3 set low successfully\r\n")
37+
uart.write_all(b"\rGPIOA pin3 set low successfully (PASS)\r\n")
3838
.unwrap();
3939
}
4040
pa3.set_high().unwrap();
4141
if pa3.is_set_high().unwrap() {
42-
uart.write_all(b"\rGPIOA pin3 set high successfully\r\n")
42+
uart.write_all(b"\rGPIOA pin3 set high successfully (PASS)\r\n")
4343
.unwrap();
4444
}
4545

4646
let mut pa4 = gpioa.pa4.into_push_pull_output();
4747
pa4.set_low().unwrap();
4848
if pa4.is_set_low().unwrap() {
49-
uart.write_all(b"\rGPIOA pin4 set low successfully\r\n")
49+
uart.write_all(b"\rGPIOA pin4 set low successfully (PASS)\r\n")
5050
.unwrap();
5151
}
5252
pa4.set_high().unwrap();
5353
if pa4.is_set_high().unwrap() {
54-
uart.write_all(b"\rGPIOA pin4 set high successfully\r\n")
54+
uart.write_all(b"\rGPIOA pin4 set high successfully (PASS)\r\n")
5555
.unwrap();
5656
}
5757
}
@@ -90,12 +90,12 @@ pub fn test_gpio_bmc_reset(uart: &mut UartController<'_>) {
9090
let mut pm5 = gpiom.pm5.into_push_pull_output();
9191
pm5.set_low().unwrap();
9292
if pm5.is_set_low().unwrap() {
93-
uart.write_all(b"\r\nGPIOM pin5 set low successfully\r\n")
93+
uart.write_all(b"\r\nGPIOM pin5 set low successfully (PASS)\r\n")
9494
.unwrap();
9595
}
9696
pm5.set_high().unwrap();
9797
if pm5.is_set_high().unwrap() {
98-
uart.write_all(b"\r\nGPIOM pin5 set high successfully\r\n")
98+
uart.write_all(b"\r\nGPIOM pin5 set high successfully (PASS)\r\n")
9999
.unwrap();
100100
}
101101
}
@@ -111,12 +111,12 @@ pub fn test_gpio_bmc_reset(uart: &mut UartController<'_>) {
111111
let mut ph2 = gpioh.ph2.into_push_pull_output();
112112
ph2.set_low().unwrap();
113113
if ph2.is_set_low().unwrap() {
114-
uart.write_all(b"\r\nGPIOH pin2 set low successfully\r\n")
114+
uart.write_all(b"\r\nGPIOH pin2 set low successfully (PASS)\r\n")
115115
.unwrap();
116116
}
117117
ph2.set_high().unwrap();
118118
if ph2.is_set_high().unwrap() {
119-
uart.write_all(b"\r\nGPIOH pin2 set high successfully\r\n")
119+
uart.write_all(b"\r\nGPIOH pin2 set high successfully (PASS)\r\n")
120120
.unwrap();
121121
}
122122
}

‎src/tests/functional/hash_test.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -93,9 +93,9 @@ where
9393

9494
if let Some(expected) = expected {
9595
if output.as_ref() == expected {
96-
writeln!(uart, "\r\n{}: Test passed!", core::any::type_name::<A>()).unwrap();
96+
writeln!(uart, "\r\n{}: Test PASS", core::any::type_name::<A>()).unwrap();
9797
} else {
98-
writeln!(uart, "\r\n{}: Test failed!", core::any::type_name::<A>()).unwrap();
98+
writeln!(uart, "\r\n{}: Test FAIL", core::any::type_name::<A>()).unwrap();
9999
writeln!(uart, "Expected:").unwrap();
100100
print_hex_array(uart, expected, 16);
101101
writeln!(uart, "Got:").unwrap();

‎src/tests/functional/hmac_test.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,9 +99,9 @@ where
9999

100100
if let Some(expected) = expected {
101101
if output.as_ref() == expected {
102-
writeln!(uart, "\r\n{}: Test passed!", core::any::type_name::<A>()).unwrap();
102+
writeln!(uart, "\r\n{}: Test PASS", core::any::type_name::<A>()).unwrap();
103103
} else {
104-
writeln!(uart, "\r\n{}: Test failed!", core::any::type_name::<A>()).unwrap();
104+
writeln!(uart, "\r\n{}: Test FAIL", core::any::type_name::<A>()).unwrap();
105105
writeln!(uart, "Expected:").unwrap();
106106
print_hex_array(uart, expected, 16);
107107
writeln!(uart, "Got:").unwrap();

‎src/tests/functional/i2c_test.rs‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -129,18 +129,18 @@ pub fn test_i2c_master(uart: &mut UartController<'_>) {
129129
if true {
130130
match i2c1.hardware.write(addr, &buf) {
131131
Ok(val) => {
132-
writeln!(uart, "i2c write ok: {val:?}\r").unwrap();
132+
writeln!(uart, "i2c write PASS: {val:?}\r").unwrap();
133133
}
134134
Err(e) => {
135-
writeln!(uart, "i2c write err: {e:?}\r").unwrap();
135+
writeln!(uart, "i2c write FAIL: {e:?}\r").unwrap();
136136
}
137137
}
138138
match i2c1.hardware.read(addr, &mut buf) {
139139
Ok(val) => {
140-
writeln!(uart, "i2c read ok: {val:?}\r").unwrap();
140+
writeln!(uart, "i2c read PASS: {val:?}\r").unwrap();
141141
}
142142
Err(e) => {
143-
writeln!(uart, "i2c read err: {e:?}\r").unwrap();
143+
writeln!(uart, "i2c read FAIL: {e:?}\r").unwrap();
144144
}
145145
}
146146
writeln!(uart, "after read data {:#x}, expected: 0x81\r\n", buf[0]).unwrap();
@@ -152,18 +152,18 @@ pub fn test_i2c_master(uart: &mut UartController<'_>) {
152152
buf[0] = off;
153153
match i2c1.hardware.write(addr, &buf) {
154154
Ok(val) => {
155-
writeln!(uart, "i2c write ok: {val:?}\r").unwrap();
155+
writeln!(uart, "i2c write PASS: {val:?}\r").unwrap();
156156
}
157157
Err(e) => {
158-
writeln!(uart, "i2c write err: {e:?}\r").unwrap();
158+
writeln!(uart, "i2c write FAIL: {e:?}\r").unwrap();
159159
}
160160
}
161161
match i2c1.hardware.read(addr, &mut buf) {
162162
Ok(val) => {
163-
writeln!(uart, "i2c read ok: {val:?}\r").unwrap();
163+
writeln!(uart, "i2c read PASS: {val:?}\r").unwrap();
164164
}
165165
Err(e) => {
166-
writeln!(uart, "i2c read err: {e:?}\r").unwrap();
166+
writeln!(uart, "i2c read FAIL: {e:?}\r").unwrap();
167167
}
168168
}
169169
writeln!(
@@ -178,28 +178,28 @@ pub fn test_i2c_master(uart: &mut UartController<'_>) {
178178
let buf2 = [0x82, 0x3];
179179
match i2c1.hardware.write(addr, &buf2) {
180180
Ok(val) => {
181-
writeln!(uart, "i2c write ok: {val:?}\r").unwrap();
181+
writeln!(uart, "i2c write PASS: {val:?}\r").unwrap();
182182
}
183183
Err(e) => {
184-
writeln!(uart, "i2c write err: {e:?}\r").unwrap();
184+
writeln!(uart, "i2c write FAIL: {e:?}\r").unwrap();
185185
}
186186
}
187187
buf[0] = 0x82;
188188
writeln!(uart, "########### read 0x82 \r\n").unwrap();
189189
match i2c1.hardware.write(addr, &buf) {
190190
Ok(val) => {
191-
writeln!(uart, "i2c write ok: {val:?}\r").unwrap();
191+
writeln!(uart, "i2c write PASS: {val:?}\r").unwrap();
192192
}
193193
Err(e) => {
194-
writeln!(uart, "i2c write err: {e:?}\r").unwrap();
194+
writeln!(uart, "i2c write FAIL: {e:?}\r").unwrap();
195195
}
196196
}
197197
match i2c1.hardware.read(addr, &mut buf) {
198198
Ok(val) => {
199-
writeln!(uart, "i2c read ok: {val:?}\r").unwrap();
199+
writeln!(uart, "i2c read PASS: {val:?}\r").unwrap();
200200
}
201201
Err(e) => {
202-
writeln!(uart, "i2c read err: {e:?}\r").unwrap();
202+
writeln!(uart, "i2c read FAIL: {e:?}\r").unwrap();
203203
}
204204
}
205205
writeln!(
@@ -286,10 +286,10 @@ pub fn test_i2c_slave(uart: &mut UartController<'_>) {
286286
.i2c_aspeed_slave_register(TEST_TARGET.address, None)
287287
{
288288
Ok(val) => {
289-
writeln!(uart, "i2c slave register ok: {val:?}\r").unwrap();
289+
writeln!(uart, "i2c slave register PASS: {val:?}\r").unwrap();
290290
}
291291
Err(e) => {
292-
writeln!(uart, "i2c slave register err: {e:?}\r").unwrap();
292+
writeln!(uart, "i2c slave register FAIL: {e:?}\r").unwrap();
293293
}
294294
}
295295

‎src/tests/functional/rsa_test.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -90,10 +90,10 @@ where
9090
continue;
9191
}
9292

93-
writeln!(uart, "\rRSA vector[{i}] sign passed").ok();
93+
writeln!(uart, "\rRSA vector[{i}] sign PASS").ok();
9494
}
9595
Err(_err) => {
96-
writeln!(uart, "\rRSA vector[{i}] sign failed").ok();
96+
writeln!(uart, "\rRSA vector[{i}] sign FAIL").ok();
9797
}
9898
}
9999
}
@@ -170,10 +170,10 @@ where
170170

171171
match result {
172172
Ok(_decrypted) => {
173-
writeln!(uart, "\rRSA vector[{i}] verify passed").ok();
173+
writeln!(uart, "\rRSA vector[{i}] verify PASS").ok();
174174
}
175175
Err(err) => {
176-
writeln!(uart, "\rRSA vector[{i}] verify failed: {err:?}").ok();
176+
writeln!(uart, "\rRSA vector[{i}] verify FAIL: {err:?}").ok();
177177
}
178178
}
179179
}

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