lcb: Defined multiple subreg index to allow aliases (#463)

* lcb: Defined multiple subreg index to allow aliases

* lcb: Fixed sub register indices

* chore: Make CheckStyle happy

* lcb: Updated tests

Author: kper

vadl/main/resources/templates/lcb/llvm/lib/Target/RegisterInfo.td

@@ -1,7 +1,12 @@
-// SubRegIndexes for GPR registers
-def SUB_32   : SubRegIndex<32>;
-def SUB_32_HI : SubRegIndex<32, 32>;
-def FULL_64    : SubRegIndex<64>;
+[# th:each="index : ${sub32}" ]
+def [(${index})]  : SubRegIndex<32>;
+[/]
+[# th:each="index : ${sub32Hi}" ]
+def [(${index})] : SubRegIndex<32, 32>;
+[/]
+[# th:each="index : ${full64}" ]
+def [(${index})]    : SubRegIndex<64>;
+[/]
 
 [# th:each="register, iterStat : ${aliasRegisters}" ]
 def [(${register.name})] : Register<"[(${register.name})]">

vadl/main/vadl/gcb/passes/GenerateCompilerRegistersPass.java

@@ -109,9 +109,11 @@ private void createSubRegisters(List<CompilerRegisterClass> aliasRegisterClasses
             var realRegister = registerClass.registers().get(i);
 
             if (hasEqualType && artificialResource.type().equals(BitsType.bits(64))) {
-              realRegister.addSubReg(aliasRegister, CompilerRegister.SubRegIndex.FULL_64);
+              realRegister.addSubReg(aliasRegister, new CompilerRegister.SubRegIndex(
+                  CompilerRegister.SubRegIndexEnum.FULL_64));
             } else {
-              realRegister.addSubReg(aliasRegister, CompilerRegister.SubRegIndex.SUB_32);
+              realRegister.addSubReg(aliasRegister, new CompilerRegister.SubRegIndex(
+                  CompilerRegister.SubRegIndexEnum.SUB_32));
             }
           }
         }

vadl/main/vadl/gcb/valuetypes/CompilerRegister.java

@@ -18,6 +18,7 @@
 
 import java.util.ArrayList;
 import java.util.List;
+import java.util.Objects;
 
 /**
  * Extends the register with information which a compiler requires.
@@ -26,14 +27,14 @@ public abstract class CompilerRegister {
   /**
    * Indicates the indices for sub registers.
    */
-  public enum SubRegIndex {
+  public enum SubRegIndexEnum {
     SUB_32("sub_32"),
     SUB_32_HI("sub_32_hi"),
     FULL_64("full_64");
 
     private final String name;
 
-    SubRegIndex(String name) {
+    SubRegIndexEnum(String name) {
       this.name = name;
     }
 
@@ -42,6 +43,51 @@ public String getName() {
     }
   }
 
+  /**
+   * Represents an index for a sub register.
+   */
+  public static class SubRegIndex {
+    private final SubRegIndexEnum subRegIndex;
+    private int version = 0;
+
+    public SubRegIndex(SubRegIndexEnum subRegIndex) {
+      this.subRegIndex = subRegIndex;
+    }
+
+    public SubRegIndexEnum inner() {
+      return subRegIndex;
+    }
+
+    /**
+     * Get the name of the register.
+     */
+    public String name() {
+      if (version == 0) {
+        return subRegIndex.name();
+      } else {
+        return subRegIndex.name() + "_" + version;
+      }
+    }
+
+    public void incrementVersion() {
+      version++;
+    }
+
+    @Override
+    public boolean equals(Object o) {
+      if (o == null || getClass() != o.getClass()) {
+        return false;
+      }
+      SubRegIndex that = (SubRegIndex) o;
+      return version == that.version && subRegIndex == that.subRegIndex;
+    }
+
+    @Override
+    public int hashCode() {
+      return Objects.hash(subRegIndex, version);
+    }
+  }
+
   protected final String name;
   protected final String asmName;
   protected final List<String> altNames;

vadl/main/vadl/lcb/passes/llvmLowering/tablegen/model/register/TableGenRegister.java

@@ -55,7 +55,8 @@ public Map<String, Object> renderObj() {
     map.put("subRegs",
         subRegs.stream().map(CompilerRegister::name).collect(Collectors.joining(", ")));
     map.put("subRegIndices",
-        subRegIndices.stream().map(Enum::name).collect(Collectors.joining(", ")));
+        subRegIndices.stream().map(CompilerRegister.SubRegIndex::name)
+            .collect(Collectors.joining(", ")));
     index.ifPresent(integer -> map.put("index", integer));
     return map;
   }

vadl/main/vadl/lcb/template/lib/Target/EmitRegisterInfoTableGenFilePass.java

@@ -130,10 +130,35 @@ protected Map<String, Object> createVariables(final PassResults passResults,
     }
 
     var registers = sortRegisters(output.registers());
+
+    var sub32 = new ArrayList<String>();
+    var sub32Hi = new ArrayList<String>();
+    var full64 = new ArrayList<String>();
+
+    for (var register : registers) {
+      var seen = new HashSet<String>();
+      for (var subRegIndex : register.subRegIndices()) {
+        if (seen.contains(subRegIndex.name())) {
+          subRegIndex.incrementVersion();
+        }
+
+        var name = subRegIndex.name();
+        seen.add(name);
+        switch (subRegIndex.inner()) {
+          case SUB_32 -> sub32.add(name);
+          case FULL_64 -> full64.add(name);
+          case SUB_32_HI -> sub32Hi.add(name);
+        }
+      }
+    }
+
     return Map.of(CommonVarNames.NAMESPACE,
         lcbConfiguration().targetName().value().toLowerCase(),
         "pointerAlignment", DataLayoutProvider.pointerAlignment(abi),
         "registers", registers,
+        "sub32", sub32.stream().distinct().toList(),
+        "sub32Hi", sub32Hi.stream().distinct().toList(),
+        "full64", full64.stream().distinct().toList(),
         "aliasRegisters", output.aliasRegisters(),
         "registerFiles", outputRegisterClasses,
         "aliasRegisterFiles", outputAliasRegisterClasses