Merge pull request #469 from OpenVADL/bugfix/temp

lcb: Use aliases for register classes

Author: kper

vadl/main/resources/templates/lcb/llvm/lib/Target/InstrInfo.cpp

@@ -123,8 +123,19 @@ static [(${namespace})]CC::CondCode getCondFromBranchOpc(unsigned Opc) {
 void [(${namespace})]InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const
 {
   [# th:each="r : ${copyPhysInstructions}" ]
-  if ( [(${namespace})]::[(${r.destRegisterFile})]RegClass.contains( DestReg )
-                && [(${namespace})]::[(${r.srcRegisterFile})]RegClass.contains( SrcReg ) )
+  if ( (
+    [# th:each="dest,iterStat : ${r.destRegisterFile}" ]
+    [#th:block th:if="${!iterStat.first}"] || [/th:block]
+      [(${namespace})]::[(${dest})]RegClass.contains( DestReg )
+    [/]
+    )
+                &&
+    (
+    [# th:each="src,iterStat : ${r.srcRegisterFile}" ]
+    [#th:block th:if="${!iterStat.first}"] || [/th:block]
+      [(${namespace})]::[(${src})]RegClass.contains( SrcReg )
+    [/]
+    ))
     {
         BuildMI( MBB, MBBI, DL, get( [(${namespace})]::[(${r.instruction})] ) )
             .addReg( DestReg, RegState::Define )

vadl/main/vadl/lcb/template/lib/Target/EmitInstrInfoCppFilePass.java

@@ -49,7 +49,9 @@
 import vadl.pass.PassResults;
 import vadl.template.Renderable;
 import vadl.types.BuiltInTable;
+import vadl.viam.ArtificialResource;
 import vadl.viam.Definition;
+import vadl.viam.GeneratesRegisterFileName;
 import vadl.viam.Instruction;
 import vadl.viam.PseudoInstruction;
 import vadl.viam.RegisterTensor;
@@ -95,8 +97,8 @@ protected String getOutputPath() {
    * @param destRegisterFile is the register file for the destination register in LLVM.
    */
   record CopyPhysRegInstruction(Instruction instruction,
-                                RegisterTensor srcRegisterFile,
-                                RegisterTensor destRegisterFile) {
+                                List<GeneratesRegisterFileName> srcRegisterFile,
+                                List<GeneratesRegisterFileName> destRegisterFile) {
   }
 
   /**
@@ -121,10 +123,11 @@ record LoadRegSlot(Instruction instruction, RegisterTensor destRegisterFile, int
 
   }
 
-  private List<CopyPhysRegInstruction> getMovInstructions(
+  private List<CopyPhysRegInstruction> physInstructions(
+      Specification viam,
       Map<MachineInstructionLabel, List<Instruction>> isaMatching) {
-    var addi32 = mapWithInstructionLabel(MachineInstructionLabel.ADDI_32, isaMatching);
-    var addi64 = mapWithInstructionLabel(MachineInstructionLabel.ADDI_64, isaMatching);
+    var addi32 = mapWithInstructionLabel(viam, MachineInstructionLabel.ADDI_32, isaMatching);
+    var addi64 = mapWithInstructionLabel(viam, MachineInstructionLabel.ADDI_64, isaMatching);
 
     return Stream.concat(addi32.stream(), addi64.stream()).toList();
   }
@@ -177,6 +180,7 @@ private List<LoadRegSlot> getLoadMemoryInstructions(
   }
 
   private List<CopyPhysRegInstruction> mapWithInstructionLabel(
+      Specification viam,
       MachineInstructionLabel label,
       Map<MachineInstructionLabel, List<Instruction>> isaMatching) {
     var instructions =
@@ -189,13 +193,34 @@ private List<CopyPhysRegInstruction> mapWithInstructionLabel(
                       .filter(HasRegisterTensor::hasRegisterFile)
                       .findFirst(),
                   "There must be destination register").registerTensor();
+
+          var destAliases = viam.isa().get().artificialResources()
+              .stream()
+              .filter(x -> x.aliasSlice() == null)
+              .filter(ArtificialResource::isRegisterFile)
+              .filter(x -> x.innerResourceRef() == destRegisterFile)
+              .toList();
+
           var srcRegisterFile =
               ensurePresent(i.behavior().getNodes(ReadsRegisterTensor.class)
                       .filter(HasRegisterTensor::hasRegisterFile)
                       .findFirst(),
                   "There must be source register").registerTensor();
 
-          return new CopyPhysRegInstruction(i, srcRegisterFile, destRegisterFile);
+          var srcAliases = viam.isa().get().artificialResources()
+              .stream()
+              .filter(x -> x.aliasSlice() == null)
+              .filter(ArtificialResource::isRegisterFile)
+              .filter(x -> x.innerResourceRef() == destRegisterFile)
+              .toList();
+
+          List<GeneratesRegisterFileName> srcResult = new ArrayList<>(srcAliases);
+          srcResult.add(srcRegisterFile);
+
+          List<GeneratesRegisterFileName> destResult = new ArrayList<>(destAliases);
+          destResult.add(destRegisterFile);
+
+          return new CopyPhysRegInstruction(i, srcResult, destResult);
         })
         .toList();
   }
@@ -337,7 +362,7 @@ protected Map<String, Object> createVariables(final PassResults passResults,
     var map = new HashMap<String, Object>();
     map.put(CommonVarNames.NAMESPACE, lcbConfiguration().targetName().value().toLowerCase());
     map.put("copyPhysInstructions",
-        getMovInstructions(isaMatches).stream().map(this::map).toList());
+        physInstructions(specification, isaMatches).stream().map(this::map).toList());
     map.put("storeStackSlotInstructions",
         getStoreMemoryInstructions(isaMatches).stream().map(this::map).toList());
     map.put("loadStackSlotInstructions",
@@ -466,8 +491,10 @@ private static void machineInstructions(
 
   private Map<String, Object> map(CopyPhysRegInstruction obj) {
     return Map.of(
-        "destRegisterFile", obj.destRegisterFile.simpleName(),
-        "srcRegisterFile", obj.srcRegisterFile.simpleName(),
+        "destRegisterFile",
+        obj.destRegisterFile.stream().map(x -> x.identifier().simpleName()).toList(),
+        "srcRegisterFile",
+        obj.srcRegisterFile.stream().map(x -> x.identifier().simpleName()).toList(),
         "instruction", obj.instruction.simpleName()
     );
   }