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AndreasKrallAndreasKrall
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Merge branch 'master' of github.com:OpenVADL/open-vadl
2 parents 7e5dac4 + 4f2a637 commit 93e0ff6

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12 files changed

+267
-134
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12 files changed

+267
-134
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‎vadl/main/resources/templates/lcb/llvm/lib/Target/DAGToDAGISel.cpp‎

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -69,13 +69,13 @@ void [(${namespace})]DAGToDAGISel::Select(SDNode *Node)
6969
}
7070

7171
static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
72-
MVT XLenVT, const [(${namespace})]Subtarget &Subtarget) {
72+
MVT VT, const [(${namespace})]Subtarget &Subtarget) {
7373
auto Seq = [(${namespace})]MatInt::generateInstSeq(Imm);
7474

7575
SDNode *Result;
7676
for ([(${namespace})]MatInt::Inst &Inst : Seq) {
77-
SDValue SDImm = CurDAG->getTargetConstant(Inst.getImm(), DL, XLenVT);
78-
Result = CurDAG->getMachineNode(Inst.getOpcode(), DL, XLenVT, SDImm);
77+
SDValue SDImm = CurDAG->getTargetConstant(Inst.getImm(), DL, VT);
78+
Result = CurDAG->getMachineNode(Inst.getOpcode(), DL, VT, SDImm);
7979
}
8080

8181
return Result;
@@ -108,12 +108,8 @@ bool [(${namespace})]DAGToDAGISel::trySelect(SDNode *Node)
108108

109109
// Handle rest
110110
int64_t Imm = ConstNode->getSExtValue();
111-
if (XLenVT == MVT::[(${stackPointerType})]) {
112-
ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT, *Subtarget));
113-
return true;
114-
}
115-
116-
return false;
111+
ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, VT, *Subtarget));
112+
return true;
117113
}
118114
default:
119115
return false;

‎vadl/main/resources/templates/lcb/llvm/lib/Target/ISelLowering.cpp‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -60,8 +60,8 @@ void [(${namespace})]TargetLowering::anchor() {}
6060

6161
[#th:block th:if="${mergedCmpAndBranch}"]
6262
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
63-
setOperationAction(ISD::BR_CC, MVT::[(${stackPointerType})], Custom);
64-
setOperationAction(ISD::SELECT_CC, MVT::[(${stackPointerType})], Custom);
63+
setOperationAction(ISD::BR_CC, { [(${branchTypes})] }, Custom);
64+
setOperationAction(ISD::SELECT_CC, { [(${branchTypes})] }, Custom);
6565
setOperationAction(ISD::SETCC, MVT::[(${stackPointerType})], Expand);
6666
[/th:block]
6767
[#th:block th:if="${!mergedCmpAndBranch}"]
@@ -82,8 +82,10 @@ const char *[(${namespace})]TargetLowering::getTargetNodeName(unsigned Opcode) c
8282
return "[(${namespace})]ISD::RetFlag";
8383
case [(${namespace})]ISD::CALL:
8484
return "[(${namespace})]ISD::CALL";
85-
case [(${namespace})]ISD::SELECT_CC:
86-
return "[(${namespace})]ISD::SELECT_CC";
85+
[# th:each="rg : ${registerFiles}" ]
86+
case [(${namespace})]ISD::SELECT_CC_[(${rg.registerFileRef.name})]:
87+
return "[(${namespace})]ISD::SELECT_CC_[(${rg.registerFileRef.name})]";
88+
[/]
8789
case [(${namespace})]ISD::LGA:
8890
return "[(${namespace})]ISD::LGA";
8991
default:
@@ -878,7 +880,7 @@ SDValue [(${namespace})]TargetLowering::lowerSelect(SDValue Op, SelectionDAG &DA
878880
// lowered SELECT_CC to take advantage of the integer
879881
// compare+branch instructions. i.e.:
880882
// (select (setcc lhs, rhs, cc), truev, falsev)
881-
// -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
883+
// -> ([(${namespace})]isd::select_cc lhs, rhs, cc, truev, falsev)
882884
if (Op.getSimpleValueType() == MVT::[(${stackPointerType})] && CondV.getOpcode() == ISD::SETCC &&
883885
CondV.getOperand(0).getSimpleValueType() == MVT::[(${stackPointerType})])
884886
{
@@ -892,7 +894,7 @@ SDValue [(${namespace})]TargetLowering::lowerSelect(SDValue Op, SelectionDAG &DA
892894
SDValue TargetCC = DAG.getConstant(CCVal, DL, MVT::[(${stackPointerType})]);
893895
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
894896
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
895-
return DAG.getNode([(${namespace})]ISD::SELECT_CC, DL, VTs, Ops);
897+
return DAG.getNode([(${namespace})]ISD::SELECT_CC_[(${mainRegisterFile.registerFileRef.name})], DL, VTs, Ops);
896898
}
897899

898900
// Otherwise:
@@ -904,7 +906,7 @@ SDValue [(${namespace})]TargetLowering::lowerSelect(SDValue Op, SelectionDAG &DA
904906
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
905907
SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
906908

907-
return DAG.getNode([(${namespace})]ISD::SELECT_CC, DL, VTs, Ops);
909+
return DAG.getNode([(${namespace})]ISD::SELECT_CC_[(${mainRegisterFile.registerFileRef.name})], DL, VTs, Ops);
908910
}
909911

910912
MachineBasicBlock *
@@ -920,6 +922,7 @@ MachineBasicBlock *
920922
llvm_unreachable("Unexpected instr type to insert");
921923
[# th:each="rg : ${registerFiles}" ]
922924
case [(${namespace})]::SelectCC_[(${rg.registerFileRef.name})]:
925+
{
923926
// To "insert" a SELECT instruction, we actually have to insert the triangle
924927
// control-flow pattern. The incoming instruction knows the destination vreg
925928
// to set, the condition code register to branch on, the true/false values to
@@ -976,6 +979,7 @@ MachineBasicBlock *
976979

977980
MI.eraseFromParent(); // The pseudo instruction is gone now.
978981
return TailMBB;
982+
}
979983
break;
980984
[/]
981985
}

‎vadl/main/resources/templates/lcb/llvm/lib/Target/ISelLowering.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,9 @@ namespace llvm
1515
FIRST_NUMBER = ISD::BUILTIN_OP_END,
1616
CALL,
1717
RET_FLAG,
18-
SELECT_CC,
18+
[# th:each="rg : ${registerFiles}" ]
19+
SELECT_CC_[(${rg.registerFileRef.name})],
20+
[/]
1921
LGA = ISD::FIRST_TARGET_MEMORY_OPCODE
2022
};
2123
}

‎vadl/main/resources/templates/lcb/llvm/lib/Target/InstrInfo.td‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -138,8 +138,11 @@ def [(${callInstruction})] : Instruction
138138
def SDT_[(${namespace})]SelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
139139
SDTCisSameAs<0, 4>,
140140
SDTCisSameAs<4, 5>]>;
141-
def target_selectcc : SDNode<"[(${namespace})]ISD::SELECT_CC", SDT_[(${namespace})]SelectCC,
141+
142+
[#th:block th:each="registerFile : ${registerFiles}" ]
143+
def target_selectcc_[(${registerFile.name})] : SDNode<"[(${namespace})]ISD::SELECT_CC_[(${registerFile.name})]", SDT_[(${namespace})]SelectCC,
142144
[SDNPInGlue]>;
145+
[/th:block]
143146

144147
def vadl_imm32 : ImmLeaf<i32, [{ return true; }]>, Operand<i32>
145148
{
@@ -171,7 +174,7 @@ def SelectCC_[(${registerFile.name})]: Instruction {
171174

172175
dag OutOperandList = (outs [(${registerFile.name})]:$dst);
173176
dag InOperandList = (ins [(${registerFile.name})]:$lhs, [(${registerFile.name})]:$rhs, vadl_imm32:$imm, [(${registerFile.name})]:$truev, [(${registerFile.name})]:$falsev);
174-
let Pattern = [ (set [(${registerFile.name})]:$dst, (target_selectcc [(${registerFile.name})]:$lhs, [(${registerFile.name})]:$rhs,
177+
let Pattern = [ (set [(${registerFile.name})]:$dst, (target_selectcc_[(${registerFile.name})] [(${registerFile.name})]:$lhs, [(${registerFile.name})]:$rhs,
175178
(i32 vadl_imm32:$imm), [(${registerFile.name})]:$truev, [(${registerFile.name})]:$falsev)) ];
176179

177180
let TSFlags{4-0} = 0;
@@ -197,7 +200,7 @@ def SelectCC_[(${registerFile.name})]: Instruction {
197200

198201
dag OutOperandList = (outs [(${registerFile.name})]:$dst);
199202
dag InOperandList = (ins [(${registerFile.name})]:$lhs, [(${registerFile.name})]:$rhs, vadl_imm64:$imm, [(${registerFile.name})]:$truev, [(${registerFile.name})]:$falsev);
200-
let Pattern = [ (set [(${registerFile.name})]:$dst, (target_selectcc [(${registerFile.name})]:$lhs, [(${registerFile.name})]:$rhs,
203+
let Pattern = [ (set [(${registerFile.name})]:$dst, (target_selectcc_[(${registerFile.name})] [(${registerFile.name})]:$lhs, [(${registerFile.name})]:$rhs,
201204
(i64 vadl_imm64:$imm), [(${registerFile.name})]:$truev, [(${registerFile.name})]:$falsev)) ];
202205

203206
let TSFlags{4-0} = 0;

‎vadl/main/vadl/lcb/passes/llvmLowering/tablegen/model/register/TableGenRegisterClass.java‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,11 @@
1717
package vadl.lcb.passes.llvmLowering.tablegen.model.register;
1818

1919
import java.util.List;
20+
import java.util.Map;
2021
import java.util.stream.Collectors;
2122
import vadl.gcb.valuetypes.TargetName;
2223
import vadl.gcb.valuetypes.ValueType;
24+
import vadl.template.Renderable;
2325
import vadl.viam.GeneratesRegisterFileName;
2426
import vadl.viam.RegisterTensor;
2527

@@ -32,12 +34,24 @@ public record TableGenRegisterClass(TargetName namespace,
3234
int alignment,
3335
List<ValueType> regTypes,
3436
List<TableGenRegister> registers,
35-
GeneratesRegisterFileName registerFileRef) {
37+
GeneratesRegisterFileName registerFileRef) implements
38+
Renderable {
3639
public String regTypesString() {
3740
return regTypes.stream().map(ValueType::getLlvmType).collect(Collectors.joining(", "));
3841
}
3942

4043
public List<ValueType> regTypes() {
4144
return regTypes;
4245
}
46+
47+
@Override
48+
public Map<String, Object> renderObj() {
49+
return Map.of(
50+
"name", name(),
51+
"regTypes", regTypes(),
52+
"registerFileRef", Map.of(
53+
"name", registerFileRef().identifier().simpleName()
54+
)
55+
);
56+
}
4357
}

‎vadl/main/vadl/lcb/template/lib/Target/EmitISelLoweringCppFilePass.java‎

Lines changed: 20 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
import java.util.List;
2525
import java.util.Map;
2626
import java.util.function.Supplier;
27-
import javax.annotation.Nullable;
27+
import java.util.stream.Stream;
2828
import vadl.configuration.LcbConfiguration;
2929
import vadl.error.Diagnostic;
3030
import vadl.error.DiagnosticBuilder;
@@ -33,20 +33,17 @@
3333
import vadl.gcb.passes.ValueRange;
3434
import vadl.gcb.passes.ValueRangeCtx;
3535
import vadl.gcb.valuetypes.ValueType;
36-
import vadl.lcb.passes.isaMatching.IsaMachineInstructionMatchingPass;
3736
import vadl.lcb.passes.isaMatching.database.Database;
3837
import vadl.lcb.passes.isaMatching.database.Query;
3938
import vadl.lcb.passes.isaMatching.database.QueryResult;
4039
import vadl.lcb.passes.llvmLowering.GenerateTableGenRegistersPass;
4140
import vadl.lcb.passes.llvmLowering.ISelLoweringOperationActionPass;
4241
import vadl.lcb.passes.llvmLowering.domain.LlvmMachineInstructionUtil;
43-
import vadl.lcb.passes.llvmLowering.tablegen.model.register.TableGenRegisterClass;
4442
import vadl.lcb.template.CommonVarNames;
4543
import vadl.lcb.template.LcbTemplateRenderingPass;
4644
import vadl.pass.PassResults;
4745
import vadl.template.Renderable;
4846
import vadl.viam.Abi;
49-
import vadl.viam.Instruction;
5047
import vadl.viam.RegisterTensor;
5148
import vadl.viam.Specification;
5249

@@ -92,8 +89,12 @@ public String llvmResultType() {
9289
protected Map<String, Object> createVariables(final PassResults passResults,
9390
Specification specification) {
9491
var abi = (Abi) specification.definitions().filter(x -> x instanceof Abi).findFirst().get();
95-
var registerFiles = ((GenerateTableGenRegistersPass.Output) passResults.lastResultOf(
96-
GenerateTableGenRegistersPass.class)).registerClasses();
92+
var generateTableGenRegistersPassOutput =
93+
((GenerateTableGenRegistersPass.Output) passResults.lastResultOf(
94+
GenerateTableGenRegistersPass.class));
95+
var registerFiles =
96+
Stream.concat(generateTableGenRegistersPassOutput.registerClasses().stream(),
97+
generateTableGenRegistersPassOutput.aliasRegisterClasses().stream()).toList();
9798
var framePointer = renderRegister(abi.framePointer().registerFile(), abi.framePointer().addr());
9899
var stackPointer = renderRegister(abi.stackPointer().registerFile(), abi.stackPointer().addr());
99100
var absoluteAddressLoadInstruction = abi.absoluteAddressLoad();
@@ -107,7 +108,10 @@ protected Map<String, Object> createVariables(final PassResults passResults,
107108

108109
var map = new HashMap<String, Object>();
109110
map.put(CommonVarNames.NAMESPACE, lcbConfiguration().targetName().value().toLowerCase());
110-
map.put("registerFiles", registerFiles.stream().map(this::mapRegisterFile).toList());
111+
map.put("registerFiles", registerFiles);
112+
map.put("mainRegisterFile",
113+
registerFiles.stream().filter(x -> x.regTypes().get(0).equals(stackPointerType)).findFirst()
114+
.get());
111115
map.put("framePointer", framePointer);
112116
map.put("stackPointer", stackPointer);
113117
map.put("stackPointerByteSize", abi.stackPointer().registerFile().resultType().bitWidth() / 8);
@@ -130,6 +134,7 @@ protected Map<String, Object> createVariables(final PassResults passResults,
130134
map.put("conditionalValueRangeLowest", conditionalValueRange.lowest());
131135
map.put("conditionalValueRangeHighest", conditionalValueRange.highest());
132136
map.put("expandableDagNodes", coverageSummary.notCoveredSelectionDagNodes());
137+
map.put("branchTypes", branchTypes(stackPointerType));
133138
map.put("mergedCmpAndBranch",
134139
!database.run(
135140
new Query.Builder().machineInstructionLabels(List.of(
@@ -181,6 +186,14 @@ protected Map<String, Object> createVariables(final PassResults passResults,
181186
return map;
182187
}
183188

189+
private String branchTypes(ValueType stackPointerType) {
190+
if (stackPointerType == ValueType.I64) {
191+
return "MVT::i32, MVT::i64";
192+
} else {
193+
return "MVT::i32";
194+
}
195+
}
196+
184197
private String getFirstNameOrEmpty(QueryResult result) {
185198
return result.machineInstructions().stream().map(x -> x.identifier().simpleName()).findFirst()
186199
.orElse("");
@@ -301,14 +314,4 @@ private Map<String, Object> mapLlvmRegisterClass(LlvmRegisterFile registerFile)
301314
"llvmResultType", registerFile.llvmResultType()
302315
);
303316
}
304-
305-
private Map<String, Object> mapRegisterFile(TableGenRegisterClass registerFile) {
306-
return Map.of(
307-
"name", registerFile.name(),
308-
"regTypes", registerFile.regTypes(),
309-
"registerFileRef", Map.of(
310-
"name", registerFile.registerFileRef().identifier().simpleName()
311-
)
312-
);
313-
}
314317
}

‎vadl/main/vadl/lcb/template/lib/Target/EmitISelLoweringHeaderFilePass.java‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,9 @@
1818

1919
import java.io.IOException;
2020
import java.util.Map;
21+
import java.util.stream.Stream;
2122
import vadl.configuration.LcbConfiguration;
23+
import vadl.lcb.passes.llvmLowering.GenerateTableGenRegistersPass;
2224
import vadl.lcb.template.CommonVarNames;
2325
import vadl.lcb.template.LcbTemplateRenderingPass;
2426
import vadl.pass.PassResults;
@@ -48,7 +50,14 @@ protected String getOutputPath() {
4850
@Override
4951
protected Map<String, Object> createVariables(final PassResults passResults,
5052
Specification specification) {
53+
var generateTableGenRegistersPassOutput =
54+
((GenerateTableGenRegistersPass.Output) passResults.lastResultOf(
55+
GenerateTableGenRegistersPass.class));
56+
var registerFiles =
57+
Stream.concat(generateTableGenRegistersPassOutput.registerClasses().stream(),
58+
generateTableGenRegistersPassOutput.aliasRegisterClasses().stream()).toList();
5159
return Map.of(CommonVarNames.NAMESPACE,
52-
lcbConfiguration().targetName().value().toLowerCase());
60+
lcbConfiguration().targetName().value().toLowerCase(),
61+
"registerFiles", registerFiles);
5362
}
5463
}

‎vadl/main/vadl/lcb/template/lib/Target/EmitInstrInfoTableGenFilePass.java‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
import vadl.lcb.passes.llvmLowering.GenerateTableGenAbiSequenceInstructionRecordPass;
3333
import vadl.lcb.passes.llvmLowering.GenerateTableGenMachineInstructionRecordPass;
3434
import vadl.lcb.passes.llvmLowering.GenerateTableGenPseudoInstructionRecordPass;
35+
import vadl.lcb.passes.llvmLowering.GenerateTableGenRegistersPass;
3536
import vadl.lcb.passes.llvmLowering.LlvmLoweringPass;
3637
import vadl.lcb.passes.llvmLowering.compensation.CompensationPatternPass;
3738
import vadl.lcb.passes.llvmLowering.immediates.GenerateTableGenImmediateRecordPass;
@@ -46,12 +47,12 @@
4647
import vadl.lcb.passes.llvmLowering.tablegen.model.TableGenPseudoInstExpansionPattern;
4748
import vadl.lcb.passes.llvmLowering.tablegen.model.TableGenPseudoInstruction;
4849
import vadl.lcb.passes.llvmLowering.tablegen.model.TableGenSelectionWithOutputPattern;
50+
import vadl.lcb.passes.llvmLowering.tablegen.model.register.TableGenRegisterClass;
4951
import vadl.lcb.template.CommonVarNames;
5052
import vadl.lcb.template.LcbTemplateRenderingPass;
5153
import vadl.pass.PassResults;
5254
import vadl.viam.Abi;
5355
import vadl.viam.PseudoInstruction;
54-
import vadl.viam.RegisterTensor;
5556
import vadl.viam.Specification;
5657

5758
/**
@@ -163,6 +164,15 @@ protected Map<String, Object> createVariables(final PassResults passResults,
163164
.filter(x -> !x.equals("\n"))
164165
.toList();
165166

167+
var generateTableGenRegistersPassOutput =
168+
((GenerateTableGenRegistersPass.Output) passResults.lastResultOf(
169+
GenerateTableGenRegistersPass.class));
170+
var registerFiles =
171+
Stream.concat(generateTableGenRegistersPassOutput.registerClasses().stream(),
172+
generateTableGenRegistersPassOutput.aliasRegisterClasses().stream())
173+
.map(this::map)
174+
.toList();
175+
166176
var map = new HashMap<String, Object>();
167177
map.put(CommonVarNames.NAMESPACE,
168178
lcbConfiguration().targetName().value().toLowerCase());
@@ -178,9 +188,7 @@ protected Map<String, Object> createVariables(final PassResults passResults,
178188
map.put("compiler", renderedTableGenCompilerInstructionsRecords);
179189
map.put("instAliases", renderedTableGenInstAliases);
180190
map.put("patterns", renderedPatterns);
181-
map.put("registerFiles",
182-
specification.registerTensors().filter(RegisterTensor::isRegisterFile).map(this::map)
183-
.toList());
191+
map.put("registerFiles", registerFiles);
184192
map.put("returnInstruction", abi.returnSequence().identifier().simpleName());
185193
map.put("callInstruction", abi.callSequence().identifier().simpleName());
186194
map.put("isCallInstructionPseudo", abi.callSequence() instanceof PseudoInstruction ? 1 : 0);
@@ -189,10 +197,10 @@ protected Map<String, Object> createVariables(final PassResults passResults,
189197
return map;
190198
}
191199

192-
private Map<String, Object> map(RegisterTensor obj) {
200+
private Map<String, Object> map(TableGenRegisterClass obj) {
193201
return Map.of(
194-
"resultWidth", obj.resultType().bitWidth(),
195-
"name", obj.simpleName()
202+
"resultWidth", obj.registerFileRef().resultType().bitWidth(),
203+
"name", obj.name()
196204
);
197205
}
198206
}

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