rtl: Automate RTL benchmarking

Author: rascmatt

docker/rtl/test-base/Dockerfile

@@ -6,6 +6,7 @@ FROM ubuntu:22.04 AS build
 SHELL ["/bin/bash", "-c"]
 
 # Install some basic utilities
+ENV DEBIAN_FRONTEND=noninteractive
 RUN apt update &&  \
     apt install -y \
     curl \
@@ -14,7 +15,8 @@ RUN apt update &&  \
     git \
     autoconf \
     build-essential \
-    python3
+    python3 \
+    opensta
 
 # Install SDKMAN, GraalVM & SBT
 RUN curl -s "https://get.sdkman.io" | bash
@@ -87,8 +89,3 @@ RUN make isa
 
 RUN mkdir /rtl
 WORKDIR /rtl
-
-# TODO:
-# Yosys
-# OpenSTA -> We can use the existing Docker image
-# Yosys + OpenSTA *.tcl Build scripts

vadl/main/resources/templates/rtl/CoreEmit.scala

@@ -21,4 +21,18 @@ class CoreEmit extends AnyFunSpec with ChiselSim {
     )
     Files.writeString(Paths.get("build/[(${topModule})].sv"), sv)
   }
+
+  it("emitDecode") {
+    Files.createDirectories(Path.of("build"))
+    val sv = ChiselStage.emitSystemVerilog(
+      new DECODE,
+      firtoolOpts = Array(
+        "--lowering-options=disallowPackedArrays,disallowLocalVariables",
+        "--strip-debug-info",
+        "--extract-test-code",
+        "--disable-layers=Verification"
+      )
+    )
+    Files.writeString(Paths.get("build/DECODE.sv"), sv)
+  }
 }

vadl/test/resources/scripts/rtl/bench/bench.sh

@@ -0,0 +1,20 @@
+#!/bin/bash
+
+# Preserve exit code when piping to tee
+set -o pipefail
+
+# Workdir is /rtl, where the OpenVADL 'rtl' output is mounted
+cd /rtl
+
+# Translate Chisel to Verilog, writes the result to build/*
+sbt "testOnly CoreEmit -- -z emit"
+
+# Run the respective yosys synthesize scripts
+yosys -s /scripts/bench/yosys/bench_decode.ys | tee build/synth_decode.log
+
+# TODO: enable spike synthesis (takes too long)
+#yosys -s /scripts/bench/yosys/bench_spike.ys | tee build/synth_spike.log
+
+# Timing analysis with OpenSTA
+sta < /scripts/bench/opensta/time_decode.tcl | tee /build/time_decode.log
+