feat(clockGate): support disable ClockGate with parameters (#451)

Users can disable clockGate by modify coupledL2 parameters.

Example:
case EnableL2ClockGate => false

Author: klin02

src/main/scala/coupledL2/CoupledL2.scala

@@ -39,6 +39,7 @@ trait HasCoupledL2Parameters {
   val p: Parameters
   // val tl2tlParams: HasTLL2Parameters = p(L2ParamKey)
   def enableCHI = p(EnableCHI)
+  def enableClockGate = p(EnableL2ClockGate)
   def cacheParams = p(L2ParamKey)
   def EnablePrivateClint = cacheParams.EnablePrivateClint
 

src/main/scala/coupledL2/DataStorage.scala

@@ -75,7 +75,8 @@ class DataStorage(implicit p: Parameters) extends L2Module {
     readMCP2 = true,
     hasMbist = p(L2ParamKey).hasMbist,
     hasSramCtl = p(L2ParamKey).hasSramCtl,
-    extraHold = true
+    extraHold = enableClockGate,
+    withClockGate = enableClockGate
   ))
   array.io_en := io.en
   private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "L2DataStorage", p(L2ParamKey).hasMbist)

src/main/scala/coupledL2/L2Param.scala

@@ -28,6 +28,7 @@ import coupledL2.prefetch._
 import utility.{MemReqSource, ReqSourceKey, Code}
 
 case object EnableCHI extends Field[Boolean](false)
+case object EnableL2ClockGate extends Field[Boolean](true)
 
 // L1 Cache Params, used for TestTop generation
 case class L1Param

src/main/scala/coupledL2/utils/GatedSplittedSRAM.scala

@@ -18,7 +18,8 @@ class GatedSplittedSRAM[T <: Data]
   singlePort: Boolean = true, bypassWrite: Boolean = false,
   clkDivBy2: Boolean = false, readMCP2: Boolean = true,
   hasMbist:Boolean = false, hasSramCtl: Boolean = false,
-  extraHold: Boolean = false, suffix: Option[String] = None
+  extraHold: Boolean = false, suffix: Option[String] = None,
+  withClockGate: Boolean = true,
 )(implicit valName: sourcecode.FullName) extends SplittedSRAM[T](
   gen = gen,
   set = set,
@@ -35,25 +36,27 @@ class GatedSplittedSRAM[T <: Data]
   hasMbist = hasMbist,
   hasSramCtl = hasSramCtl,
   extraHold = extraHold,
-  extClockGate = true,
+  extClockGate = withClockGate,
   suffix = Some(suffix.getOrElse(SramHelper.getSramSuffix(valName.value)))
 ) {
   // en is the actual r/w valid (last for one cycle)
   // en is used to generate gated_clock for each SRAM
   val io_en = IO(Input(Bool()))
 
   // Create a ClockGate module for each element in the array
-  array.map(_.map(_.map(a => {
-    val cg = Module(new MbistClockGateCell(extraHold))
-    cg.E := io_en
-    cg.dft.fromBroadcast(a.io.broadcast.getOrElse(0.U.asTypeOf(new SramBroadcastBundle)))
-    cg.mbist.req := a.io.mbistCgCtl.map(_.en).getOrElse(false.B)
-    cg.mbist.writeen := a.io.mbistCgCtl.map(_.wckEn).getOrElse(false.B)
-    cg.mbist.readen := a.io.mbistCgCtl.map(_.rckEn).getOrElse(false.B)
-    a.io.mbistCgCtl.foreach(_.wclk := cg.out_clock)
-    a.io.mbistCgCtl.foreach(_.rclk := cg.out_clock)
-    a.clock := clock
-  })))
+  if (withClockGate) {
+    array.map(_.map(_.map(a => {
+      val cg = Module(new MbistClockGateCell(extraHold))
+      cg.E := io_en
+      cg.dft.fromBroadcast(a.io.broadcast.getOrElse(0.U.asTypeOf(new SramBroadcastBundle)))
+      cg.mbist.req := a.io.mbistCgCtl.map(_.en).getOrElse(false.B)
+      cg.mbist.writeen := a.io.mbistCgCtl.map(_.wckEn).getOrElse(false.B)
+      cg.mbist.readen := a.io.mbistCgCtl.map(_.rckEn).getOrElse(false.B)
+      a.io.mbistCgCtl.foreach(_.wclk := cg.out_clock)
+      a.io.mbistCgCtl.foreach(_.rclk := cg.out_clock)
+      a.clock := clock
+    })))
+  }
 
   // TODO: for now, all small SRAMs use the unified `io_en` signal for gating.
   // Theoretically, gating can be set based on whether the small SRAM is activated