Merge branch 'master' into feat-l1hint

Author: bosscharlie

.github/workflows/main.yml

@@ -67,25 +67,11 @@ jobs:
       - name: Compile
         run: make compile
 
-      # Clean artifacts folder (./tl-test-new/run) after successful run
-      - name: Unit Test for TileLink version
-        run: |
-            git clone https://github.com/OpenXiangShan/tl-test-new
-            cd ./tl-test-new
-            sed -i 's/ari.target.*/ari.target = 240/g' ./configs/user.tltest.ini
-            rm -rf ./dut/CoupledL2 && ln -s ../.. ./dut/CoupledL2
-            make coupledL2-test-l2l3l2 run THREADS_BUILD=4 CXX_COMPILER=clang++-17
-            rm -rf run/*.vcd run/*.fst run/*.log run/*.db
-
-      - name: Tar up artifacts of Unit Test for TileLink version
-        if: always()
-        run: |
-            test -d ./tl-test-new/run || mkdir -p ./tl-test-new/run
-            tar -zcf ${{ env.RUN_ARCHIVE_TL }} ./tl-test-new/run
-
       # Clean artifacts folder (./tl-test-new/run) after successful run
       - name: Unit test for CHI version
         run: |
+            rm -rf tl-test-new
+            git clone https://github.com/OpenXiangShan/tl-test-new
             cd ./tl-test-new
             sed -i 's/ari.target.*/ari.target = 240/g' ./configs/user.tltest.ini
             sed -i 's/cmo.enable .*=.*/cmo.enable = 1/g' ./configs/user.tltest.ini
@@ -105,6 +91,23 @@ jobs:
         run: |
             test -d ./tl-test-new/run || mkdir -p ./tl-test-new/run
             tar -zcf ${{ env.RUN_ARCHIVE_CHI }} ./tl-test-new/run
+      
+      # Clean artifacts folder (./tl-test-new/run) after successful run
+      - name: Unit Test for TileLink version
+        run: |
+            rm -rf tl-test-new
+            git clone https://github.com/OpenXiangShan/tl-test-new
+            cd ./tl-test-new
+            sed -i 's/ari.target.*/ari.target = 240/g' ./configs/user.tltest.ini
+            rm -rf ./dut/CoupledL2 && ln -s ../.. ./dut/CoupledL2
+            make coupledL2-test-l2l3l2 run THREADS_BUILD=4 CXX_COMPILER=clang++-17
+            rm -rf run/*.vcd run/*.fst run/*.log run/*.db
+
+      - name: Tar up artifacts of Unit Test for TileLink version
+        if: always()
+        run: |
+            test -d ./tl-test-new/run || mkdir -p ./tl-test-new/run
+            tar -zcf ${{ env.RUN_ARCHIVE_TL }} ./tl-test-new/run
 
       - name: Upload artifacts of Unit Test
         if: always()

src/main/scala/coupledL2/CustomL1Hint.scala

@@ -123,9 +123,11 @@ class CustomL1Hint(implicit p: Parameters) extends L2Module {
   hint_s1Queue.io.enq.bits.source := enqSource_s1
   hint_s1Queue.io.enq.bits.isKeyword := enqKeyWord_s1
   hint_s1Queue.io.deq.ready := hintQueue.io.enq.ready && !enqValid_s3
-  // WARNING:TODO: ensure queue will never overflow
-  // assert(hint_s1Queue.io.enq.ready, "hint_s1Queue should never be full")
-  // assert(hintQueue.io.enq.ready, "hintQueue should never be full")
+  
+  assert(hint_s1Queue.io.enq.ready, "hint_s1Queue should never be full")
+  // *NOTICE: 'hintQueue' is now possible to be full and backpressing 'hint_s1Queue'.
+  //          Hence, this assertion here was currently unnecessary and overkilled.
+  //assert(hintQueue.io.enq.ready, "hintQueue should never be full")
 
   val hintDropValid = hintQueue.io.deq.valid && hintDropQueue.io.deq.valid && hintQueue.io.deq.bits.source === hintDropQueue.io.deq.bits.source
 

src/main/scala/coupledL2/L2Param.scala

@@ -119,8 +119,8 @@ case class L2Param(
   enableTagECC: Boolean = false,
   enableDataECC: Boolean = false,
   // DataCheck
-  dataCheck: Option[String] = None,
-  enablePoison: Boolean = false,
+  dataCheck: Option[String] = Some("oddparity"),
+  enablePoison: Boolean = true,
 
   // Network layer SAM
   sam: Seq[(AddressSet, Int)] = Seq(AddressSet.everything -> 0)

src/main/scala/coupledL2/tl2chi/MMIOBridge.scala

@@ -160,17 +160,18 @@ class MMIOBridgeEntry(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CHIL2Mo
     val dataCheck = if (enableDataCheck) {
       dataCheckMethod match {
         case 1 => (0 until DATACHECK_WIDTH).map(i =>
-          rxdat.bits.dataCheck.get(i) ^ rdata(8 * (i + 1) - 1, 8 * i).xorR ^ true.B).reduce(_ | _)
+          rxdat.bits.dataCheck.get(i) ^ rxdat.bits.data(8 * (i + 1) - 1, 8 * i).xorR ^ true.B).reduce(_ | _)
         case 2 =>
           val code = new SECDEDCode
           (0 until DATACHECK_WIDTH).map(i =>
-            code.decode(Cat(rxdat.bits.dataCheck.get(i) ^ rdata(8 * (i + 1) - 1, 8 * i))).error).reduce(_ | _)
+            code.decode(Cat(rxdat.bits.dataCheck.get(i) ^ rxdat.bits.data(8 * (i + 1) - 1, 8 * i))).error).reduce(_ | _)
         case _ => false.B
       }
     } else {
       false.B
     }
     val poison = rxdat.bits.poison.getOrElse(false.B).orR
+    assert(!(dataCheck || poison), "UC should not have DataCheck/Poison error")
     denied := denied || nderr
     corrupt := corrupt || derr || nderr || dataCheck || poison
   }

src/main/scala/coupledL2/tl2chi/MSHR.scala

@@ -1103,6 +1103,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   when (rxdat.valid) {
     val nderr = rxdat.bits.respErr.getOrElse(OK) === NDERR
     val derr = rxdat.bits.respErr.getOrElse(OK) === DERR
+    val rxdatCorrupt = rxdat.bits.corrupt
     ifAfterIssueC {
       when (rxdat.bits.chiOpcode.get === DataSepResp) {
         require(beatSize == 2) // TODO: This is ugly
@@ -1113,7 +1114,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
         gotDirty := gotDirty || rxdatIsU_PD
         gotGrantData := true.B
         denied := denied || nderr
-        corrupt := corrupt || derr || nderr
+        corrupt := corrupt || derr || nderr || rxdatCorrupt
       }
     }
 

src/main/scala/coupledL2/tl2chi/RXDAT.scala

@@ -52,6 +52,7 @@ class RXDAT(implicit p: Parameters) extends TL2CHIL2Module {
     false.B
   }
   val poison = io.out.bits.poison.getOrElse(false.B).orR
+  assert(!((dataCheck || poison) && io.out.valid), "RXDAT(cached) should not have DataCheck/Poison error")
 
   /* Write Refill Buffer*/
   io.refillBufWrite.valid := io.out.valid