Bump coupledL2 upstream at Dec 19, 2025

Merge coupledL2 commits up to 95e8de (2025-12-01),
which is tracking by XiangShan commit c06233 (2025-12-08).

Squashed commit of the following:

commit 95e8de9
Author: lwd <liuweiding10@outlook.com>
Date:   Mon Dec 1 11:44:38 2025 +0800

        fix(AsyncBridge): revert (OpenXiangShan#433) (OpenXiangShan#446)

        Revert "fix(AsyncBridge): add l-credit manager in AsyncBridge to fix performance (OpenXiangShan#433)"

        This reverts commit 4fc8217.

commit cfc9235
Author: zhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>
Date:   Tue Nov 25 16:54:40 2025 +0800

        Timing(TL2CHICoupledL2): remove ICG of 'pCrdGrantType' and 'pCrdGrantSrcID' (OpenXiangShan#444)

        Co-authored-by: Zhu Yu <yulightenyu@gmail.com>

commit 7ea02e3
Author: Yanqin Li <maxpicca@qq.com>
Date:   Tue Nov 25 15:03:42 2025 +0800

        time(bop): fix long path due to clock gating (OpenXiangShan#442)

commit a9990de
Author: Ma-YX <71326427+Ma-YX@users.noreply.github.com>
Date:   Mon Nov 24 15:11:48 2025 +0800

        fix(MainPipe, MSHR, RXDAT): not report DataCheck error to BEU (OpenXiangShan#443)

        When detected Data Check error in RXDAT,
        coupledL2 reports corrupt = 1(TL) to L1 $,
        but not reports L2 Error to BEU.
        Prioritize triggering synchronous exceptions
        over asynchronous ones.

commit d00d32f
Author: yanyiming <139243183+Yan-Yiming@users.noreply.github.com>
Date:   Mon Nov 10 22:21:19 2025 +0800

        perf: add perfevent (OpenXiangShan#441)

        add perfevent for last level cache event:
            l2_cache_prefetch_{access, miss}
            l2_cache_{access, miss}_{rd, wr}

            add perfevent for cache hit/miss in L2:
            l2_cache_hit, l2_cache_miss

commit 4fc8217
Author: yulightenyu <145419941+yulightenyu@users.noreply.github.com>
Date:   Fri Nov 7 17:23:32 2025 +0800

        fix(AsyncBridge): add l-credit manager in AsyncBridge to fix performance (OpenXiangShan#433)

        - For rx channel, add l-credit manager module to generate 'lcrdv' right after rx flit received
        - For tx channel, add l-credit manager module to generate 'ready' to block tx flit, using l-credit
          number more than Maximum tx l-credit in CoupledL2 to cover lcrdv sync delay

commit f4b7db3
Author: Ding Haonan <kumonda@kucro3.org>
Date:   Fri Nov 7 17:21:51 2025 +0800

        fix(MainPipe, MSHR): decode SnpPreferUnique as SnpUnique (OpenXiangShan#438)

commit c1022d9
Author: Ding Haonan <kumonda@kucro3.org>
Date:   Fri Nov 7 17:18:16 2025 +0800

        timing(LinkLayer, RXSNP): simplified CMO on RXSNP and pipelined RXRSP, RXDAT (OpenXiangShan#436)

        * timing(RXSNP): CMO blocks RXSNP regardless of PA for better timing

        ### 1. **In the past**:

        - RXSNP (with same address) was blocked for CMO when:
          - In progress of Probing L1
          - Ready to send ```WriteBackFull```/```WriteCleanFull```/```Evict```,
            but not sent yet (more specifically, went through S3 of MainPipe)
          - In progress of compensational meta write (more specifically,
            changing ```TRUNK``` to ```TIP```)

        - **```blockRefill```** means: ready to send ```WriteBackFull```/
          ```WriteCleanFull```/```Evict```, but not sent yet (more specifically,
          went through S3 of MainPipe)

        - **```w_releaseack```** means: ready to receive ```CompDBIDResp``` from
          downstream

        - **```s_cmometaw```** means compensational meta write, changing
          ```TRUNK``` to ```TIP``` in L2 and not initiating any
          ```WriteBackFull```/```WriteCleanFull```/```Evict``` (CoupledL2 now is
          not sending any ```Probe toT``` to L1, so no ```TRUNK``` state could
          be kept in L2 after any CMO)

        - By **```reqBlockSnpMask```**, blocking RXSNP (with same address) for
          CMO when:
          - Before ```WriteBackFull```/```WriteCleanFull```/```Evict``` sent, or
            after ```CompDBIDResp``` received, in progress of Probing L1
          - Before ```WriteBackFull```/```WriteCleanFull```/```Evict``` sent, or
            after ```CompDBIDResp``` received, in progress of compensational
            meta write (more specifically, changing ```TRUNK``` to ```TIP```)

        - By **```cmoBlockSnpMask```**, blocking RXSNP (with same address) for
          CMO when:
          - Ready to send ```WriteBackFull```/```WriteCleanFull```/```Evict```,
            but not sent yet (more specifically, went through S3 of MainPipe)
          - In progress of Probing L1

        - In **```reqBlockSnpMask```** and **```cmoBlockSnpMask```**:
          - Blockage by progress of Probing L1 was duplicated
          - Blockage by compensational meta write was duplicated
          - Blockage constraint (Before ```WriteBackFull```/```WriteCleanFull```
            /```Evict``` sent, After ```CompDBIDResp``` received) was
            unnecessary, since:
            - The first constraint (Before ```WriteBackFull```/
              ```WriteCleanFull```/```Evict``` sent) was unnecessary since:
              - RXSNP must always be blocked in progress of Probing L1
              - The compensational meta write ```cmometaw``` activity is equal
                to the attempt to send ```WriteBackFull```/```WriteCleanFull```/
                ```Evict``` in MSHR sequence (```cmometaw``` would only and
                immediately be activated after MSHR decided not to send any
                ```WriteBackFull```/```WriteCleanFull```/```Evict```)
            - The second constraint (After ```CompDBIDResp``` received) was kept
              by HN / L3

        ### 2. **After this PR**:

        - All duplicated blocking logic would be removed, and all blocking logic
          would be merged into **```cmoBlockSnpMask```**, blocking RXSNP for CMO
          when:
          - In progress of Probing L1
          - Ready to send ```WriteBackFull```/```WriteCleanFull```/```Evict```,
            but not sent yet (more specifically, went through S3 of MainPipe)
          - In progress of compensational meta write (more specifically,
            changing ```TRUNK``` to ```TIP```)

        - PA would be no longer taken into consideration for timing reason, but
          would still be dead-lock free, since:
          - Progress of Probing L1 is not depending on any downstream sequence
          - Progress of sending TXREQ is not depending on any downstream
            sequence

        * timing(TL2CHICoupledL2): add pipeline(deppth=1, pipe=1) on rxdat/rxrsp channel

        ---------

        Co-authored-by: Zhu Yu <yulightenyu@gmail.com>

commit 826415a
Author: yanyiming <139243183+Yan-Yiming@users.noreply.github.com>
Date:   Fri Nov 7 17:09:38 2025 +0800

        perf: add perfevent (OpenXiangShan#437)

        add perfevent for last level cache event:
        l2_cache_prefetch_{access, miss}
        l2_cache_{access, miss}_{rd, wr}

        add perfevent for cache hit/miss in L2:
        l2_cache_hit, l2_cache_miss

Author: Wonicon

HuanCun

@@ -5,6 +5,8 @@ NUM_SLICE ?= 4
 WITH_CHISELDB ?= 1
 WITH_TLLOG ?= 1
 WITH_CHILOG ?= 1
+BY_ETIME ?= 1
+BY_VTIME ?= 0
 FPGA ?= 0
 
 init:
@@ -16,11 +18,13 @@ compile:
 
 CHI_PASS_ARGS = ISSUE=$(ISSUE) NUM_CORE=$(NUM_CORE) NUM_TL_UL=$(NUM_TL_UL) NUM_SLICE=$(NUM_SLICE) \
 			    WITH_CHISELDB=$(WITH_CHISELDB) WITH_TLLOG=$(WITH_TLLOG) WITH_CHILOG=$(WITH_CHILOG) \
+				BY_ETIME=$(BY_ETIME) BY_VTIME=$(BY_VTIME) \
 			    FPGA=$(FPGA)
 
 TOP = TestTop
 CHI_TOP_ARGS = --issue $(ISSUE) --core $(NUM_CORE) --tl-ul $(NUM_TL_UL) --bank $(NUM_SLICE) \
 		   	   --chiseldb $(WITH_CHISELDB) --tllog $(WITH_TLLOG) --chilog $(WITH_CHILOG) \
+			   --etime $(BY_ETIME) --vtime $(BY_VTIME) \
 		       --fpga $(FPGA)
 BUILD_DIR = ./build
 TOP_V = $(BUILD_DIR)/$(TOP).sv

Makefile

@@ -12,9 +12,8 @@ import $file.`rocket-chip`.hardfloat.build
 val defaultScalaVersion = "2.13.15"
 
 def defaultVersions = Map(
-  "chisel"        -> ivy"org.chipsalliance::chisel:6.6.0",
-  "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:6.6.0",
-  "chiseltest"    -> ivy"edu.berkeley.cs::chiseltest:6.0.0"
+  "chisel"        -> ivy"org.chipsalliance::chisel:7.0.0",
+  "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:7.0.0"
 )
 
 trait HasChisel extends ScalaModule {
@@ -69,7 +68,11 @@ object utility extends SbtModule with HasChisel {
   override def millSourcePath = os.pwd / "utility"
 
   override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
- }
+
+  override def ivyDeps = super.ivyDeps() ++ Agg(
+    ivy"com.lihaoyi::sourcecode:0.4.4",
+  )
+}
 
 object huancun extends SbtModule with HasChisel {
   override def millSourcePath = os.pwd / "HuanCun"
@@ -88,11 +91,7 @@ object CoupledL2 extends SbtModule with HasChisel with millbuild.common.CoupledL
 
   def huancunModule: ScalaModule = huancun
 
-  object test extends SbtModuleTests with TestModule.ScalaTest {
-    override def ivyDeps = super.ivyDeps() ++ Agg(
-      defaultVersions("chiseltest"),
-    )
-  }
+  object test extends SbtModuleTests with TestModule.ScalaTest
 
   override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
 

build.sc

@@ -22,7 +22,7 @@ import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink.TLBundle
 import utility._
-import coupledL2.prefetch.PrefetchIO
+import coupledL2.prefetch._
 
 trait BaseOuterBundle
 
@@ -36,7 +36,7 @@ abstract class BaseSliceIO[T_OUT <: BaseOuterBundle](implicit p: Parameters) ext
   val prefetch = prefetchOpt.map(_ => Flipped(new PrefetchIO))
   // val msStatus = topDownOpt.map(_ => Vec(mshrsAll, ValidIO(new MSHRStatus)))
   val dirResult = topDownOpt.map(_ => ValidIO(new DirResult))
-  val latePF = topDownOpt.map(_ => Output(Bool()))
+  val latePF = topDownOpt.map(_ => ValidIO(UInt(PfSource.pfSourceBits.W)))
   val error = DecoupledIO(new L2CacheErrorInfo())
   val l2Miss = Output(Bool())
   val l2Flush = Option.when(cacheParams.enableL2Flush) (Input(Bool()))

rocket-chip

@@ -185,11 +185,10 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle
   val allowRetry = chiOpt.map(_ => Bool())
   val memAttr = chiOpt.map(_ => new MemAttr)
   val traceTag = chiOpt.map(_ => Bool())
-  val dataCheckErr = chiOpt.map(_ => Bool())
 
   def toCHIREQBundle(): CHIREQ = {
     val req = WireInit(0.U.asTypeOf(new CHIREQ()))
-    req.qos := Fill(QOS_WIDTH, 1.U(1.W)) // TODO
+    req.qos := Fill(QOS_WIDTH, 1.U(1.W)) - 1.U // TODO
     req.tgtID := tgtID.getOrElse(0.U)
     req.srcID := srcID.getOrElse(0.U)
     req.txnID := txnID.getOrElse(0.U)
@@ -294,7 +293,6 @@ class RespInfoBundle(implicit p: Parameters) extends L2Bundle
   val pCrdType = chiOpt.map(_ => UInt(PCRDTYPE_WIDTH.W))
   val respErr = chiOpt.map(_ => UInt(RESPERR_WIDTH.W))
   val traceTag = chiOpt.map(_ => Bool())
-  val dataCheckErr = chiOpt.map(_ => Bool())
 }
 
 class RespBundle(implicit p: Parameters) extends L2Bundle {
@@ -387,6 +385,7 @@ class PrefetchCtrlFromCore extends Bundle {
   val l2_pbop_en = Bool()
   val l2_vbop_en = Bool()
   val l2_tp_en = Bool()
+  val l2_pf_delay_latency = UInt(10.W)
 }
 
 class PrefetchRecv extends Bundle {

src/main/scala/coupledL2/BaseSlice.scala

@@ -40,6 +40,7 @@ trait HasCoupledL2Parameters {
   // val tl2tlParams: HasTLL2Parameters = p(L2ParamKey)
   def enableCHI = p(EnableCHI)
   def cacheParams = p(L2ParamKey)
+  def EnablePrivateClint = cacheParams.EnablePrivateClint
 
   def XLEN = 64
   def blocks = cacheParams.sets * cacheParams.ways
@@ -90,12 +91,12 @@ trait HasCoupledL2Parameters {
   def eccTagBankBits = encTagBankBits - tagBankBits
   def enableDataECC = cacheParams.enableDataECC
   def dataBankSplit = 4
-  def dataSRAMSplit = 8
+  def dataSRAMSplit = 4
   def wordBits = 64
   def bankWords = blockBits / wordBits / dataBankSplit
   def dataBankBits = wordBits * bankWords
   def encBankBits = cacheParams.dataCode.width(dataBankBits)
-  def encDataPadBits = 4 // recaculate if any split changes
+  def encDataPadBits = 0 // recaculate if any split changes
 
   // Prefetch
   def prefetchers = cacheParams.prefetch
@@ -145,7 +146,7 @@ trait HasCoupledL2Parameters {
   def sam = cacheParams.sam
 
   // Hardware Performance Monitor
-  def numPCntHc: Int = 12
+  def numPCntHc: Int = 17
 
   def getClientBitOH(sourceId: UInt): UInt = {
     if (clientBits == 0) {

src/main/scala/coupledL2/Common.scala

@@ -21,7 +21,8 @@ import chisel3._
 import chisel3.util._
 import utility.mbist.MbistPipeline
 import coupledL2.utils._
-import utility.{ParallelPriorityMux, RegNextN, XSPerfAccumulate, Code, SRAMTemplate}
+import utility.{ParallelPriorityMux, RegNextN, XSPerfAccumulate, Code}
+import utility.sram.SRAMTemplate
 import org.chipsalliance.cde.config.Parameters
 import coupledL2.prefetch.PfSource
 import freechips.rocketchip.tilelink.TLMessages._

src/main/scala/coupledL2/CoupledL2.scala

@@ -146,6 +146,9 @@ case class L2Param(
   // Enable sram test support
   hasMbist: Boolean = false,
   hasSramCtl: Boolean = false,
+
+  // Enable new clint
+  EnablePrivateClint: Boolean = false
 ) {
   def toCacheParams: CacheParameters = CacheParameters(
     name = name,

src/main/scala/coupledL2/Directory.scala

@@ -96,9 +96,18 @@ class RequestArb(implicit p: Parameters) extends L2Module
     mshr_task_s1.bits.opcode === Grant ||
     mshr_task_s1.bits.opcode === GrantData ||
     mshr_task_s1.bits.opcode === AccessAckData ||
-    mshr_task_s1.bits.opcode === HintAck && mshr_task_s1.bits.dsWen
+    mshr_task_s1.bits.opcode === HintAck
   )
 
+  assert(!s1_needs_replRead || mshr_task_s1.bits.opcode =/= GrantData || mshr_task_s1.bits.dsWen, 
+    "replTask of GrantData with no DataStorage write was not expected")
+
+  assert(!s1_needs_replRead || mshr_task_s1.bits.opcode =/= AccessAckData || mshr_task_s1.bits.dsWen,
+    "replTask of AccessAckData with no DataStorage write was not expected")
+  
+  assert(!s1_needs_replRead || mshr_task_s1.bits.opcode =/= HintAck || mshr_task_s1.bits.dsWen,
+    "replTask of HintAck with no DataStorage write was not expected")
+
   /* ======== Stage 0 ======== */
   // if mshr_task_s1 is replRead, it might stall and wait for dirRead.ready, so we block new mshrTask from entering
   // TODO: will cause msTask path vacant for one-cycle after replRead, since not use Flow so as to avoid ready propagation