fix(ResetGen): use ResetGen provided in utility

Tang-Haojin · Tang-Haojin · commit 7c9d4cbb2a6d · 2025-05-26T12:36:04.000+08:00
diff --git a/Utility b/Utility
@@ -1 +1 @@
-Subproject commit de50694f6ffb48780a4b4665907442b3e4dd0d6d
+Subproject commit 8ef84f12393af527dfd1dc073549fa336332eff1
diff --git a/src/main/scala/huancun/HuanCun.scala b/src/main/scala/huancun/HuanCun.scala
@@ -28,8 +28,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.util.{BundleField, BundleFieldBase, UIntToOH1}
 import huancun.prefetch._
-import utils.ResetGen
-import utility.{Pipeline, FastArbiter}
+import utility.{FastArbiter, Pipeline, ResetGen}
 import huancun.noninclusive.MSHR
 
 trait HasHuanCunParameters {
diff --git a/src/main/scala/huancun/utils/ResetGen.scala b/src/main/scala/huancun/utils/ResetGen.scala
diff --git a/src/test/scala/huancun/TestTop.scala b/src/test/scala/huancun/TestTop.scala
@@ -64,6 +64,7 @@ class TestTop_L2()(implicit p: Parameters) extends LazyModule {
     case PerfCounterOptionsKey => PerfCounterOptions(
       here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,
       false,
+      XSPerfLevel.withName("VERBOSE"),
       0
     )
   })))
@@ -168,6 +169,7 @@ class TestTop_L2_Standalone()(implicit p: Parameters) extends LazyModule {
     case PerfCounterOptionsKey => PerfCounterOptions(
       here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,
       false,
+      XSPerfLevel.withName("VERBOSE"),
       0
     )
   })))
@@ -260,6 +262,7 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {
     case PerfCounterOptionsKey => PerfCounterOptions(
       here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,
       false,
+      XSPerfLevel.withName("VERBOSE"),
       i
     )
   }))).node)
@@ -282,6 +285,7 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {
     case PerfCounterOptionsKey => PerfCounterOptions(
       here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,
       false,
+      XSPerfLevel.withName("VERBOSE"),
       0
     )
   })))
@@ -402,6 +406,7 @@ class TestTop_FullSys()(implicit p: Parameters) extends LazyModule {
     case PerfCounterOptionsKey => PerfCounterOptions(
       here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,
       false,
+      XSPerfLevel.withName("VERBOSE"),
       i
     )
   }))).node)
@@ -426,6 +431,7 @@ class TestTop_FullSys()(implicit p: Parameters) extends LazyModule {
     case PerfCounterOptionsKey => PerfCounterOptions(
       here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,
       false,
+      XSPerfLevel.withName("VERBOSE"),
       0
     )
   })))

Original file line number	Diff line number	Diff line change
`@@ -64,6 +64,7 @@ class TestTop_L2()(implicit p: Parameters) extends LazyModule {`
`64`	`64`	`case PerfCounterOptionsKey => PerfCounterOptions(`
`65`	`65`	`here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,`
`66`	`66`	`false,`
	`67`	`+ XSPerfLevel.withName("VERBOSE"),`
`67`	`68`	`0`
`68`	`69`	`)`
`69`	`70`	`})))`
`@@ -168,6 +169,7 @@ class TestTop_L2_Standalone()(implicit p: Parameters) extends LazyModule {`
`168`	`169`	`case PerfCounterOptionsKey => PerfCounterOptions(`
`169`	`170`	`here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,`
`170`	`171`	`false,`
	`172`	`+ XSPerfLevel.withName("VERBOSE"),`
`171`	`173`	`0`
`172`	`174`	`)`
`173`	`175`	`})))`
`@@ -260,6 +262,7 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {`
`260`	`262`	`case PerfCounterOptionsKey => PerfCounterOptions(`
`261`	`263`	`here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,`
`262`	`264`	`false,`
	`265`	`+ XSPerfLevel.withName("VERBOSE"),`
`263`	`266`	`i`
`264`	`267`	`)`
`265`	`268`	`}))).node)`
`@@ -282,6 +285,7 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {`
`282`	`285`	`case PerfCounterOptionsKey => PerfCounterOptions(`
`283`	`286`	`here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,`
`284`	`287`	`false,`
	`288`	`+ XSPerfLevel.withName("VERBOSE"),`
`285`	`289`	`0`
`286`	`290`	`)`
`287`	`291`	`})))`
`@@ -402,6 +406,7 @@ class TestTop_FullSys()(implicit p: Parameters) extends LazyModule {`
`402`	`406`	`case PerfCounterOptionsKey => PerfCounterOptions(`
`403`	`407`	`here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,`
`404`	`408`	`false,`
	`409`	`+ XSPerfLevel.withName("VERBOSE"),`
`405`	`410`	`i`
`406`	`411`	`)`
`407`	`412`	`}))).node)`
`@@ -426,6 +431,7 @@ class TestTop_FullSys()(implicit p: Parameters) extends LazyModule {`
`426`	`431`	`case PerfCounterOptionsKey => PerfCounterOptions(`
`427`	`432`	`here(HCCacheParamsKey).enablePerf && !here(HCCacheParamsKey).FPGAPlatform,`
`428`	`433`	`false,`
	`434`	`+ XSPerfLevel.withName("VERBOSE"),`
`429`	`435`	`0`
`430`	`436`	`)`
`431`	`437`	`})))`