feat(smcntrpmf): support Smcntrpmf extension

wissygh · wissygh · commit 57bd9052b38d · 2025-02-18T10:09:58.000+08:00
diff --git a/configs/riscv64-dual-xs-ref-debug_defconfig b/configs/riscv64-dual-xs-ref-debug_defconfig
@@ -71,6 +71,7 @@ CONFIG_RV_SSNPM=y
 CONFIG_RV_SMNPM=y
 CONFIG_RV_SMMPM=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-dual-xs-ref_defconfig b/configs/riscv64-dual-xs-ref_defconfig
@@ -72,6 +72,7 @@ CONFIG_RV_SSNPM=y
 CONFIG_RV_SMNPM=y
 CONFIG_RV_SMMPM=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs-cpt-with-flash_defconfig b/configs/riscv64-xs-cpt-with-flash_defconfig
@@ -65,6 +65,7 @@ CONFIG_RV_SMMPM=y
 CONFIG_RV_SVNAPOT=y
 CONFIG_RV_SVPBMT=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs-cpt_defconfig b/configs/riscv64-xs-cpt_defconfig
@@ -65,6 +65,7 @@ CONFIG_RV_SMMPM=y
 CONFIG_RV_SVNAPOT=y
 CONFIG_RV_SVPBMT=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs-diff-spike-withflash_defconfig b/configs/riscv64-xs-diff-spike-withflash_defconfig
@@ -73,6 +73,7 @@ CONFIG_RV_SMMPM=y
 CONFIG_RV_SVNAPOT=y
 CONFIG_RV_SVPBMT=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 # CONFIG_RV_SHLCOFIDELEG is not set
 # CONFIG_RV_SMSTATEEN is not set
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs-diff-spike_defconfig b/configs/riscv64-xs-diff-spike_defconfig
@@ -71,6 +71,7 @@ CONFIG_RV_SSNPM=y
 CONFIG_RV_SMNPM=y
 CONFIG_RV_SMMPM=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 # CONFIG_RV_SHLCOFIDELEG is not set
 # CONFIG_RV_SMSTATEEN is not set
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs-ref-debug_defconfig b/configs/riscv64-xs-ref-debug_defconfig
@@ -71,6 +71,7 @@ CONFIG_RV_SSNPM=y
 CONFIG_RV_SMNPM=y
 CONFIG_RV_SMMPM=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs-ref_bitmap_defconfig b/configs/riscv64-xs-ref_bitmap_defconfig
@@ -71,6 +71,7 @@ CONFIG_RV_SSNPM=y
 CONFIG_RV_SMNPM=y
 CONFIG_RV_SMMPM=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs_bitmap_defconfig b/configs/riscv64-xs_bitmap_defconfig
@@ -71,6 +71,7 @@ CONFIG_RV_SSNPM=y
 CONFIG_RV_SMNPM=y
 CONFIG_RV_SMMPM=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/configs/riscv64-xs_defconfig b/configs/riscv64-xs_defconfig
@@ -71,6 +71,7 @@ CONFIG_RV_SSNPM=y
 CONFIG_RV_SMNPM=y
 CONFIG_RV_SMMPM=y
 CONFIG_RV_SSCOFPMF=y
+CONFIG_RV_SMCNTRPMF=y
 CONFIG_RV_SHLCOFIDELEG=y
 CONFIG_RV_SMSTATEEN=y
 CONFIG_MISA_UNCHANGEABLE=y
diff --git a/ready-to-run b/ready-to-run
@@ -1 +1 @@
-Subproject commit c8c11d58ed9f3389874665673b29fad26a6be791
+Subproject commit a05fe3ab52307f7151ae3a679fbdd96c4107bbb7
diff --git a/src/isa/riscv64/Kconfig b/src/isa/riscv64/Kconfig
@@ -452,6 +452,10 @@ config RV_SSCOFPMF
   bool "(Beta)Enable Sscofpmf extension(Supervisor-level Count OverFlow and Privilege Mode Filtering)"
   default n
 
+config RV_SMCNTRPMF
+  bool "(Beta)Enable Smcntrpmf extension(Cycle and Instret Privilege Mode Filtering)"
+  default n
+
 config RV_SHLCOFIDELEG
   depends on RVH
   depends on RV_SSCOFPMF
diff --git a/src/isa/riscv64/local-include/csr.h b/src/isa/riscv64/local-include/csr.h
@@ -412,9 +412,18 @@
   #define CSRS_M_MCOUNTINHIBIT(f)
 #endif // CONFIG_RV_CSR_MCOUNTINHIBIT
 
+#ifdef CONFIG_RV_SMCNTRPMF
+  #define CSRS_M_SMCNTRPMF(f) \
+  f(mcyclecfg    , 0x321) \
+  f(minstretcfg  , 0x322)
+#else // CONFIG_RV_SMCNTRPMF
+  #define CSRS_M_SMCNTRPMF(f)
+#endif // CONFIG_RV_SMCNTRPMF
+
 #define CSRS_M_COUNTER_SETUP(f) \
   CSRS_M_MCOUNTINHIBIT(f) \
-  CSRS_M_HPMEVENT(f)
+  CSRS_M_HPMEVENT(f) \
+  CSRS_M_SMCNTRPMF(f)
   
 /** Debug/Trace Registers (Trigger Module Registers) **/
 #ifdef CONFIG_RV_SDTRIG
@@ -688,6 +697,22 @@ CSR_STRUCT_START(mcountinhibit)
 CSR_STRUCT_END(mcountinhibit)
 #endif // CONFIG_RV_CSR_MCOUNTINHIBIT
 
+#ifdef CONFIG_RV_SMCNTRPMF
+#define CSRS_M_SMCNTRPMF_STRUCT(name, addr) \
+  typedef union {                   \
+    struct {                        \
+      uint64_t pad0     :58;        \
+      uint64_t vuinh    : 1;        \
+      uint64_t vsinh    : 1;        \
+      uint64_t uinh     : 1;        \
+      uint64_t sinh     : 1;        \
+      uint64_t minh     : 1;        \
+    };                              \
+    word_t val;                     \
+  } concat(name, _t);
+MAP(CSRS_M_SMCNTRPMF, CSRS_M_SMCNTRPMF_STRUCT)
+#endif // CONFIG_RV_SMCNTRPMF
+
 CSR_STRUCT_START(mscratch)
 CSR_STRUCT_END(mscratch)
 
diff --git a/src/isa/riscv64/system/priv.c b/src/isa/riscv64/system/priv.c
@@ -726,39 +726,46 @@ inline word_t gen_status_sd(word_t status) {
   return ((word_t)(fs_dirty || vs_dirty)) << 63;
 }
 
+#ifdef CONFIG_RV_SMCNTRPMF
+static inline bool inbibit_smcntrpmf(word_t current_cfg) {
+  bool inbibit = false;
+  mcyclecfg_t* cfg = (mcyclecfg_t*)&current_cfg;
+  inbibit = (cpu.mode == MODE_M && cfg->minh) 
+    || (cpu.mode == MODE_S && cfg->sinh) 
+    || (cpu.mode == MODE_U && cfg->uinh) 
+#ifdef CONFIG_RVH
+    || (cpu.mode == MODE_S && cpu.v && cfg->vsinh) 
+    || (cpu.mode == MODE_U && cpu.v && cfg->vuinh); 
+#endif // CONFIG_RVH
+  return inbibit;
+}
+#endif // CONFIG_RV_SMCNTRPMF
+
 static inline word_t get_mcycle() {
-  #ifdef CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
-    if (mcountinhibit->val & 0x1) {
-      return mcycle->val;
-    }
-  #endif // CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
+  bool inbibit = MUXDEF(CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR, mcountinhibit->val & 0x1, false) 
+  || MUXDEF(CONFIG_RV_SMCNTRPMF, inbibit_smcntrpmf(mcyclecfg->val), false);
+  if (inbibit) return mcycle->val;
   return mcycle->val + get_abs_instr_count_csr();
 }
 
 static inline word_t get_minstret() {
-  #ifdef CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
-    if (mcountinhibit->val & 0x4) {
-      return minstret->val;
-    }
-  #endif // CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
+  bool inbibit = MUXDEF(CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR, mcountinhibit->val & 0x4, false) 
+  || MUXDEF(CONFIG_RV_SMCNTRPMF, inbibit_smcntrpmf(minstretcfg->val), false);
+  if (inbibit) return minstret->val;
   return minstret->val + get_abs_instr_count_csr();
 }
 
 static inline word_t set_mcycle(word_t src) {
-  #ifdef CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
-    if (mcountinhibit->val & 0x1) {
-      return src;
-    }
-  #endif // CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
+  bool inbibit = MUXDEF(CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR, mcountinhibit->val & 0x1, false) 
+  || MUXDEF(CONFIG_RV_SMCNTRPMF, inbibit_smcntrpmf(mcyclecfg->val), false);
+  if (inbibit) return src;
   return src - get_abs_instr_count_csr();
 }
 
 static inline word_t set_minstret(word_t src) {
-  #ifdef CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
-    if (mcountinhibit->val & 0x4) {
-      return src;
-    }
-  #endif // CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR
+  bool inbibit = MUXDEF(CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR, mcountinhibit->val & 0x4, false) 
+  || MUXDEF(CONFIG_RV_SMCNTRPMF, inbibit_smcntrpmf(minstretcfg->val), false);
+    if (inbibit) return src;
   return src - get_abs_instr_count_csr();
 }
 
