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1 parent e3b117c commit ddb0cbcCopy full SHA for ddb0cbc
src/main/scala/utility/TLUtils/BusKeyField.scala
@@ -47,6 +47,17 @@ object MemReqSource extends Enumeration {
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val reqSourceBits = log2Ceil(ReqSourceCount.id)
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+ def isCPUReq(reqSource: UInt): Bool = {
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+ reqSource === CPULoadData.id.U ||
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+ reqSource === CPUStoreData.id.U ||
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+ reqSource === CPUAtomicData.id.U
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+ }
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+
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+ def isL1Prefetch(reqSource: UInt): Bool = {
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+ reqSource === L1InstPrefetch.id.U ||
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+ reqSource === L1DataPrefetch.id.U
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def isL2Prefetch(reqSource: UInt): Bool = {
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reqSource === Prefetch2L2BOP.id.U ||
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reqSource === Prefetch2L2PBOP.id.U ||
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