refactor(Sram): refactor SRAM DFT io ports (#115)

Author: cz4e

src/main/scala/utility/mbist/MbistClockGateCell.scala

@@ -25,10 +25,10 @@ class CgDftBundle extends Bundle {
   val ram_aux_ckbp = Input(Bool())
   val cgen = Input(Bool())
   def fromBroadcast(brc: SramBroadcastBundle): Unit = {
-    ram_aux_clk := brc.mbist.ram_aux_clk
-    ram_aux_ckbp := brc.mbist.ram_aux_ckbp
-    ram_mcp_hold := brc.mbist.ram_mcp_hold
-    cgen := brc.mbist.cgen
+    ram_aux_clk := brc.ram_aux_clk
+    ram_aux_ckbp := brc.ram_aux_ckbp
+    ram_mcp_hold := brc.ram_mcp_hold
+    cgen := brc.cgen
   }
 }
 

src/main/scala/utility/sram/SRAMTemplate.scala

@@ -367,7 +367,7 @@ class SRAMTemplate[T <: Data](
   }
 
   private val ramRdata = SramProto.read(array, singlePort, ramRaddr, ramRen)
-  private val finalRamWen = ramWen && !brcBd.mbist.ram_hold
+  private val finalRamWen = ramWen && !brcBd.ram_hold
   when(finalRamWen) {
     SramProto.write(array, singlePort, ramWaddr, ramWdata, ramWmask)
   }

src/main/scala/utility/sram/SramCtl.scala

@@ -143,7 +143,7 @@ object SramHelper {
     template: RawModule
   ): (Ram2Mbist, Instance[SramArray], String) = {
 
-    val (array, vname) = SramProto(rclk, !dp, set, sp.sramDataBits, sp.sramMaskBits, setup, hold, latency, wclk, bist || broadcast.isDefined, hasSramCtl || broadcast.isDefined, suffix)
+    val (array, vname) = SramProto(rclk, !dp, set, sp.sramDataBits, sp.sramMaskBits, setup, hold, latency, wclk, bist, hasSramCtl, suffix)
     val bdParam = Ram2MbistParams(
       sp,
       set,
@@ -164,12 +164,12 @@ object SramHelper {
     mbist.we := false.B
     mbist.re := false.B
     mbist.wmask := Fill(sp.mbistMaskWidth, true.B)
-    if(broadcast.isDefined || bist) {
-      array.mbist.get.dft_ram_bp_clken := broadcast.get.mbist.ram_bp_clken
-      array.mbist.get.dft_ram_bypass := broadcast.get.mbist.ram_bypass
+    if(bist) {
+      array.mbist.get.dft_ram_bp_clken := broadcast.get.ram_bp_clken
+      array.mbist.get.dft_ram_bypass := broadcast.get.ram_bypass
     }
-    if(broadcast.isDefined || hasSramCtl) {
-      array.sramCtl.get := broadcast.get.sramCtl
+    if(hasSramCtl) {
+      array.ram_ctl.get := broadcast.get.ram_ctl
     }
     if(bist) {
       dontTouch(mbist)

src/main/scala/utility/sram/SramHelper.scala

@@ -28,19 +28,15 @@ class SramMbistIO extends Bundle {
   val dft_ram_bp_clken = Input(Bool())
 }
 
-class SramMbistBundle extends Bundle {
-  val ram_hold     = Bool()
-  val ram_bypass   = Bool()
-  val ram_bp_clken = Bool()
-  val ram_aux_clk  = Bool()
-  val ram_aux_ckbp = Bool()
-  val ram_mcp_hold = Bool()
-  val cgen         = Bool()
-}
-
 class SramBroadcastBundle extends Bundle {
-  val mbist   = Input(new SramMbistBundle)
-  val sramCtl = Input(new SramCtlBundle)
+  val ram_hold     = Input(Bool())
+  val ram_bypass   = Input(Bool())
+  val ram_bp_clken = Input(Bool())
+  val ram_aux_clk  = Input(Bool())
+  val ram_aux_ckbp = Input(Bool())
+  val ram_mcp_hold = Input(Bool())
+  val ram_ctl      = Input(UInt(64.W))
+  val cgen         = Input(Bool())
 }
 
 @instantiable
@@ -57,8 +53,8 @@ abstract class SramArray(
   require(width % maskSegments == 0)
   @public val mbist = if(hasMbist) Some(IO(new SramMbistIO)) else None
   mbist.foreach(dontTouch(_))
-  @public val sramCtl = Option.when(hasSramCtl)(IO(Input(new SramCtlBundle)))
-  sramCtl.foreach(dontTouch(_))
+  @public val ram_ctl = Option.when(hasSramCtl)(IO(Input(UInt(64.W))))
+  ram_ctl.foreach(dontTouch(_))
 
   @public val RW0 = if(singlePort) {
     Some(IO(new Bundle() {