|
| 1 | +# XSAI Agent Notes |
| 2 | + |
| 3 | +This document is for automated coding agents working in this repo. |
| 4 | +Follow it before making changes. |
| 5 | + |
| 6 | +## Ground Rules |
| 7 | +- Primary build system: Mill (see `build.sc`), invoked via Makefile helpers. |
| 8 | +- Scala formatting: scalafmt configs live in multiple submodules; root uses `.scalafmt.conf`. |
| 9 | +- Scala style: `scalastyle-config.xml` and `scalastyle-test-config.xml` define naming, imports, and size limits. |
| 10 | + |
| 11 | +## Build, Lint, Test |
| 12 | +All commands below are from repo root unless noted. |
| 13 | + |
| 14 | +### Initialize submodules |
| 15 | +``` |
| 16 | +make init |
| 17 | +# or force re-sync submodules |
| 18 | +make init-force |
| 19 | +``` |
| 20 | + |
| 21 | +### Compile / generate Verilog |
| 22 | +``` |
| 23 | +make init # fetch required submodules first |
| 24 | +make comp # mill xiangshan.compile + xiangshan.test.compile |
| 25 | +make verilog # generate FPGA / synthesis RTL at build/rtl/XSTop.sv |
| 26 | +make sim-verilog # generate simulation RTL (SimTop, with difftest-friendly logic) |
| 27 | +``` |
| 28 | + |
| 29 | +Common build-time knobs used across `verilog`, `sim-verilog`, and `emu`: |
| 30 | +``` |
| 31 | +CONFIG=MinimalMatrixConfig # choose XSAI config; default is DefaultMatrixConfig |
| 32 | +NUM_CORES=2 # generate multi-core RTL / simulator |
| 33 | +ISSUE=E.b # CHI issue selection |
| 34 | +JVM_XMX=40G JVM_XSS=256m # tune Mill / Scala memory usage for large builds |
| 35 | +YAML_CONFIG=path/to/file.yaml # override parameters from YAML |
| 36 | +``` |
| 37 | + |
| 38 | +Useful generation notes from xs-env workflow: |
| 39 | +- `make verilog` is for FPGA / synthesis style RTL; it strips simulation-only debug pieces such as DiffTest. |
| 40 | +- `make sim-verilog` is the normal frontend for simulation RTL; `make emu`, `make simv`, and `make xsim` depend on it. |
| 41 | +- `make verilog NUM_CORES=2` generates dual-core synthesis RTL. |
| 42 | +- Long RTL generation jobs are usually run under `tmux` / `screen` on a machine with enough RAM. |
| 43 | + |
| 44 | +### Simulators |
| 45 | +``` |
| 46 | +make emu # Verilator-based simulator build (default software simulation flow) |
| 47 | +make simv # VCS-based build |
| 48 | +make xsim # GalaxSim / X-EPIC build |
| 49 | +make pldm-build # Palladium build |
| 50 | +``` |
| 51 | + |
| 52 | +Common `make emu` options worth knowing: |
| 53 | +``` |
| 54 | +make emu CONFIG=MinimalConfig EMU_THREADS=8 -j16 |
| 55 | +make emu EMU_TRACE=fst EMU_THREADS=8 RELEASE=1 -j32 |
| 56 | +make emu -j16 EMU_THREADS=8 WITH_CHISELDB=1 EMU_TRACE=fst CONFIG=DefaultMatrixConfig |
| 57 | +``` |
| 58 | + |
| 59 | +- `CONFIG=...`: choose the hardware config to elaborate. |
| 60 | +- `EMU_THREADS=<n>`: enable multi-threaded RTL simulation in Verilator; for XSAI / XiangShan AI, `8` or `16` is the preferred range for `make emu`. |
| 61 | +- `EMU_TRACE=fst|FST`: compile waveform support with FST output; smaller than VCD. |
| 62 | +- `RELEASE=1`: build a faster, more stripped-down simulator (`--fpga-platform --disable-all --remove-assert --reset-gen` path in `Makefile`). |
| 63 | +- `WITH_CHISELDB=1`, `WITH_ROLLINGDB=1`, `WITH_CONSTANTIN=1`: enable extra database / analysis facilities when needed. |
| 64 | +- `CONFIG=DefaultMatrixConfig` is a common XSAI matrix-extension configuration for emulation. |
| 65 | +- `WITH_DRAMSIM3=1 DRAMSIM3_HOME=...`: switch simulated memory model to DRAMSim3. |
| 66 | +- `WITH_RESETGEN=1`, `DISABLE_PERF=1`, `DISABLE_ALWAYSDB=1`: extra debug / performance toggles passed into `SimTop` generation. |
| 67 | +- `FIRRTL_COVER=...`: extract FIRRTL coverage when doing coverage-oriented builds. |
| 68 | + |
| 69 | +Unless otherwise specified, Verilator-based `emu` is the default recommendation. |
| 70 | + |
| 71 | +### Run a workload on `emu` |
| 72 | +Basic run: |
| 73 | +``` |
| 74 | +./build/emu -i ./ready-to-run/coremark-2-iteration.bin \ |
| 75 | + --diff ../NEMU/build/riscv64-nemu-interpreter-so |
| 76 | +``` |
| 77 | + |
| 78 | +Frequently used runtime options (from `./build/emu --help` / `difftest` args): |
| 79 | +``` |
| 80 | +-i <bin> # workload image |
| 81 | +--diff <ref.so> # reference model shared library for DiffTest |
| 82 | +--no-diff # disable DiffTest |
| 83 | +-C, --max-cycles <n> # stop after at most n cycles |
| 84 | +-I, --max-instr <n> # stop after at most n instructions |
| 85 | +-s, --seed <n> # set random seed |
| 86 | +-b, --log-begin <n> # enable log / wave window start cycle |
| 87 | +-e, --log-end <n> # enable log / wave window end cycle |
| 88 | +--dump-wave # dump waveform when log window is active |
| 89 | +--dump-wave-full # dump full waveform when log window is active |
| 90 | +--wave-path <file> # write waveform to a specific path |
| 91 | +--force-dump-result # force final perf counter dump |
| 92 | +--enable-fork # enable LightSSS-style fork debugging |
| 93 | +--dump-ref-trace # dump REF trace in the logging window |
| 94 | +--dump-commit-trace # dump commit trace in the logging window |
| 95 | +``` |
| 96 | + |
| 97 | +Typical debug / waveform commands: |
| 98 | +``` |
| 99 | +./build/emu -i ./ready-to-run/linux.bin --diff ../NEMU/build/riscv64-nemu-interpreter-so |
| 100 | +
|
| 101 | +./build/emu -i ./ready-to-run/linux.bin --diff ../NEMU/build/riscv64-nemu-interpreter-so \ |
| 102 | + -b 10000 -e 11000 --dump-wave |
| 103 | +
|
| 104 | +./build/emu -i ./ready-to-run/linux.bin --no-diff -C 500000 --force-dump-result \ |
| 105 | + 2>&1 | tee emu.log |
| 106 | +``` |
| 107 | + |
| 108 | +Waveform notes: |
| 109 | +- Wave dumping at runtime only works if waveform support was compiled in via `EMU_TRACE=...` during `make emu`. |
| 110 | +- `-b` / `-e` default to `0`; a real wave window needs `-e > -b`. |
| 111 | +- Default wave files are written under `build/`; `--wave-path` overrides that. |
| 112 | + |
| 113 | +### Lint / format |
| 114 | +``` |
| 115 | +make check-format # scalafmt check via mill xiangshan.checkFormat |
| 116 | +make reformat # scalafmt rewrite via mill xiangshan.reformat |
| 117 | +``` |
| 118 | +Submodules also have check/format targets (for example `utility/Makefile` and `coupledL2/Makefile`). |
| 119 | + |
| 120 | +## Code Style |
| 121 | +These rules combine repository conventions and scalastyle/scalafmt settings. |
| 122 | + |
| 123 | +### Formatting |
| 124 | +- Use scalafmt with max line length 120 (see `.scalafmt.conf`). |
| 125 | +- Root config uses `preset = defaultWithAlign`, `rewrite.rules = [RedundantBraces, RedundantParens, SortModifiers, Imports]`. |
| 126 | +- Trailing commas are disabled in root config. |
| 127 | +- Keep existing local `.scalafmt.conf` in submodules; do not mix versions across subprojects. |
| 128 | + |
| 129 | +### Imports |
| 130 | +- Avoid block imports (`import pkg.{a, b}`) per scalastyle. |
| 131 | +- Avoid wildcard imports (`import pkg._`) except `chisel3._` and `chisel3.util._`. |
| 132 | +- Imports are sorted using the scalastyle order (`rewrite.imports.sort = scalastyle`). |
| 133 | + |
| 134 | +### Naming |
| 135 | +- Classes/objects: UpperCamelCase. |
| 136 | +- Methods: lowerCamelCase or UpperCamelCase (methods can act as constants). |
| 137 | +- Variables/fields: lowerCamelCase; constants in objects: UpperCamelCase. |
| 138 | +- Allowed field prefixes for pipeline signals: `sx_`, `perf_`, `debug_`. |
| 139 | +- Package names: all lower-case. |
| 140 | + |
| 141 | +### Types and signatures |
| 142 | +- Public methods must have explicit type annotations (scalastyle rule). |
| 143 | +- Prefer type aliases already used in the code (see `src/main/scala/xiangshan/Parameters.scala`). |
| 144 | +- Keep implicit parameters explicit in constructors where used, e.g. `(implicit val p: Parameters)`. |
| 145 | + |
| 146 | +### Error handling and assertions |
| 147 | +- Use `require(...)` for configuration invariants (common in core modules). |
| 148 | +- Prefer `Option.when(...)` for optional IO/fields instead of nulls. |
| 149 | +- Do not swallow errors; surface with `require` or propagate via module IOs. |
| 150 | + |
| 151 | +### Chisel/RTL patterns |
| 152 | +- Use `dontTouch` only when necessary (e.g. keeping debug/flush signals). |
| 153 | +- Prefer `Decoupled`/`Valid` interfaces for handshaked signals; keep naming consistent. |
| 154 | +- Keep IO bundles in a single `IO(new Bundle { ... })` block for modules. |
| 155 | + |
| 156 | +### File hygiene |
| 157 | +- License headers are expected (see `scalastyle-config.xml`); keep the existing XiangShan header style in Scala sources. |
| 158 | +- Avoid tabs, trailing whitespace, and missing newline at EOF. |
| 159 | +- Avoid TODO/FIXME comments unless tracked and short-lived. |
| 160 | +- Avoid line-ending semicolons (`;`). |
| 161 | + |
| 162 | +## Useful entry points |
| 163 | +- Core top: `src/main/scala/xiangshan/XSCore.scala` |
| 164 | +- Global parameters: `src/main/scala/xiangshan/Parameters.scala` |
| 165 | +- L2 cache (coupledL2): `coupledL2/src/main/scala/coupledL2/CoupledL2.scala` |
| 166 | + |
| 167 | +## Commit message format |
| 168 | +- Follow the existing Conventional Commits-style summary used in this repo: `type(scope): subject` |
| 169 | +- `type` should be lowercase (common in history: `fix`, `feat`, `refactor`, `ci`, `timing`, `submodule`). |
| 170 | +- `scope` is optional but recommended for non-trivial changes (examples seen: `matrix`, `backend`, `rob`, `cache`). |
| 171 | +- Keep the subject imperative, concise, and without a trailing period; prefer <= 72 characters when possible. |
| 172 | +- The subject line is required; an optional multi-line body is allowed and recommended for non-obvious changes. |
| 173 | + |
| 174 | +Examples: |
| 175 | +- ``` |
| 176 | + fix(matrix): Reset value for xmcsr |
| 177 | +
|
| 178 | + - Root cause: xmcsr was left X after reset, causing nondeterminism in difftest |
| 179 | + - Fix: initialize xmcsr to 0 and gate reset under AME when disabled |
| 180 | + - Test: run `make emu CONFIG=DefaultMatrixConfig` with coremark and difftest enabled |
| 181 | + ``` |
| 182 | +- ``` |
| 183 | + feat(difftest): Support refill check for XSAI |
| 184 | +
|
| 185 | + - Update global mem at matrix store. |
| 186 | + - Enable Refill Check. |
| 187 | + ``` |
| 188 | +- `submodules: Bump HBL2 and difftest` |
| 189 | + |
| 190 | +## Notes for agents |
| 191 | +- This repo is large and uses submodules. Run `make init` before building. |
| 192 | +- Prefer Makefile entry points (they wrap mill with args/config). |
| 193 | +- Only build full XiangShan RTL / simulators when necessary. A full `make verilog`, `make sim-verilog`, or `make emu` often takes tens of minutes to more than an hour and can consume substantial CPU and memory; prefer targeted checks, code inspection, or narrower tests first when they are sufficient. |
| 194 | +- For XSAI / XiangShan AI, prefer `EMU_THREADS=8` or `EMU_THREADS=16` when building `make emu`, unless a task specifically needs a different setting. |
| 195 | +- Do not change build tools or formatting configs unless the task requires it. |
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