fix(no-matrix): Remove wires for diff mx when AME is disabled

Author: yu-yake2002

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -997,7 +997,7 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
       val lsdqFull  = Bool()
     }
   })
-  val diff_mx_rat  = if (params.basicDebugEn) Some(Vec(3, Output(UInt(PhyRegIdxWidth.W)))) else None
+  val diff_mx_rat  = if (params.basicDebugEn && HasMatrixExtension) Some(Vec(3, Output(UInt(PhyRegIdxWidth.W)))) else None
   val diff_vl_rat  = if (params.basicDebugEn) Some(Vec(1, Output(UInt(PhyRegIdxWidth.W)))) else None
 
   val sqCanAccept = Input(Bool())

src/main/scala/xiangshan/backend/datapath/DataPath.scala

@@ -321,15 +321,15 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
   private val v0DiffReadData: Option[Vec[UInt]] =
     OptionWrapper(backendParams.basicDebugEn, Wire(Vec(V0PhyRegs, UInt(V0Data().dataWidth.W))))
   private val mxDiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(3, UInt(log2Up(MxPhyRegs).W))), Wire(Vec(3, UInt(MxData().dataWidth.W)))))
+    OptionWrapper(backendParams.basicDebugEn && HasMatrixExtension, (Wire(Vec(3, UInt(log2Up(MxPhyRegs).W))), Wire(Vec(3, UInt(MxData().dataWidth.W)))))
   private val vlDiffRead: Option[(Vec[UInt], Vec[UInt])] =
     OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(1, UInt(log2Up(VlPhyRegs).W))), Wire(Vec(1, UInt(VlData().dataWidth.W)))))
 
   private val vecDiffNumPregs = 2 * (V0PhyRegs + vfSchdParams.numPregs)
   private val vecDiffReadData: Option[Vec[UInt]] =
     OptionWrapper(backendParams.basicDebugEn, Wire(Vec(vecDiffNumPregs, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0))
   private val mxDiffReadData: Option[Vec[UInt]] =
-    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(3, UInt(MxData().dataWidth.W))))
+    OptionWrapper(backendParams.basicDebugEn && HasMatrixExtension, Wire(Vec(3, UInt(MxData().dataWidth.W))))
   private val vlDiffReadData: Option[UInt] =
     OptionWrapper(backendParams.basicDebugEn, Wire(UInt(VlData().dataWidth.W)))
 
@@ -1094,8 +1094,8 @@ class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBund
 
   val diffVlRat  = if (params.basicDebugEn) Some(Input(Vec(1, UInt(log2Up(VlPhyRegs).W)))) else None
   val diffVl     = if (params.basicDebugEn) Some(Output(UInt(VlData().dataWidth.W))) else None
-  val diffMxRat  = if (params.basicDebugEn) Some(Input(Vec(3, UInt(log2Up(MxPhyRegs).W)))) else None
-  val diffMx     = if (params.basicDebugEn) Some(Output(Vec(3, UInt(MxData().dataWidth.W)))) else None
+  val diffMxRat  = if (params.basicDebugEn && HasMatrixExtension) Some(Input(Vec(3, UInt(log2Up(MxPhyRegs).W)))) else None
+  val diffMx     = if (params.basicDebugEn && HasMatrixExtension) Some(Output(Vec(3, UInt(MxData().dataWidth.W)))) else None
 
   val topDownInfo = new TopDownInfo
 }

src/main/scala/xiangshan/backend/rename/RenameTable.scala

@@ -253,11 +253,11 @@ class RenameTableWrapper(implicit p: Parameters) extends XSModule {
     val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None
     val debug_v0_rat  = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None
     val debug_vl_rat  = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None
-    val debug_mx_rat = if (backendParams.debugEn) Some(Vec(3,Output(UInt(PhyRegIdxWidth.W)))) else None
+    val debug_mx_rat = if (backendParams.debugEn && HasMatrixExtension) Some(Vec(3,Output(UInt(PhyRegIdxWidth.W)))) else None
 
     // for difftest
     val diff_vl_rat  = if (backendParams.basicDebugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None
-    val diff_mx_rat = if (backendParams.basicDebugEn) Some(Vec(3,Output(UInt(PhyRegIdxWidth.W)))) else None
+    val diff_mx_rat = if (backendParams.basicDebugEn && HasMatrixExtension) Some(Vec(3,Output(UInt(PhyRegIdxWidth.W)))) else None
   })
 
   val intRat = Module(new RenameTable(Reg_I))
@@ -468,8 +468,8 @@ class RenameTableWrapper(implicit p: Parameters) extends XSModule {
     io.debug_mx_rat.foreach(_ := mxRat.get.io.debug_rdata.get)
     io.diff_mx_rat.foreach(_ := mxRat.get.io.diff_rdata.get)
   } else {
-    io.debug_mx_rat.get.foreach(_ := 0.U)
-    io.diff_mx_rat.get.foreach(_ := 0.U)
+    io.debug_mx_rat.foreach(_ := 0.U)
+    io.diff_mx_rat.foreach(_ := 0.U)
   }
   mxRat.foreach(_.io.readPorts <> io.mxReadPorts.get.flatten)
   mxRat.foreach(_.io.redirect := io.redirect)