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lines changed Original file line number Diff line number Diff line change @@ -66,13 +66,13 @@ jobs:
6666 make StandAloneDebugModule DEVICE_BASE_ADDR=0x38020000 DEVICE_ADDR_WIDTH=32 DEVICE_DATA_WIDTH=64 DEVICE_TL=0 DEVICE_PREFIX=DM_
6767 make StandAlonePLIC DEVICE_BASE_ADDR=0x3C000000 DEVICE_ADDR_WIDTH=32 DEVICE_DATA_WIDTH=64 DEVICE_TL=0 DEVICE_PREFIX=PLIC_
6868 make clean
69- - name : generate XSNoCTop verilog file
70- run : |
71- python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --config XSNoCTopConfig
72- - name : check XSNoCTop verilog
73- run : |
74- python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/rtl
75- python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
69+ # - name: generate XSNoCTop verilog file
70+ # run: |
71+ # python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --config XSNoCTopConfig
72+ # - name: check XSNoCTop verilog
73+ # run: |
74+ # python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/rtl
75+ # python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
7676 - name : generate verilog file
7777 run :
7878 python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --num-cores 2
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