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fix(dispatch): Update source selection logic to conditionally include matrix extension sources
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src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -522,7 +522,11 @@ class NewDispatch(implicit p: Parameters) extends XSModule with HasPerfEvents wi
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val thisSrcHasV0 = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) V0RegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _)
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val thisSrcHasVl = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) VlRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _)
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val thisSrcHasMx = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) MxRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _)
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val selSrcState = Seq(thisSrcHasInt || maskForStd, thisSrcHasFp || maskForStd, thisSrcHasVec, thisSrcHasV0, thisSrcHasMx, thisSrcHasVl)
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val selSrcState = if (HasMatrixExtension) {
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Seq(thisSrcHasInt || maskForStd, thisSrcHasFp || maskForStd, thisSrcHasVec, thisSrcHasV0, thisSrcHasMx, thisSrcHasVl)
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} else {
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Seq(thisSrcHasInt || maskForStd, thisSrcHasFp || maskForStd, thisSrcHasVec, thisSrcHasV0, thisSrcHasVl)
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}
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IQSelUop(temp).bits.srcState(j) := PriorityMux(oh, allSrcState)(j).zip(selSrcState).filter(_._2 == true).map(_._1).foldLeft(false.B)(_ || _).asUInt
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}
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temp = temp + 1

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