Commit 13bec12
1 file changed
+1
-1
lines changed- .github/workflows/main.yml+2-2
- .github/workflows/nightly.yml+1-1
- Makefile+4-1
- README.md+1-1
- build.sc+1-1
- src/main/scala/Bundles.scala+23-16
- src/main/scala/DPIC.scala+47-30
- src/main/scala/Difftest.scala+48-5
- src/main/scala/Gateway.scala+24-12
- src/main/scala/Preprocess.scala+70-122
- src/main/scala/SimTop.scala+18-6
- src/main/scala/common/Mem.scala+21
- src/main/scala/fpga/AXI4.scala+26
- src/main/scala/fpga/Host.scala+154
- src/test/csrc/common/compress.cpp+14-4
- src/test/csrc/difftest/difftest.cpp+18-47
- src/test/csrc/difftest/difftest.h+25-47
- src/test/csrc/plugin/simfrontend/ftq.cpp+1-1
- src/test/vsrc/common/ram.v-20
- src/test/vsrc/fpga/Difftest2AXI.v-211
- src/test/vsrc/fpga/bram_port.v-52
- src/test/vsrc/fpga/dual_buffer_bram.sv-56
- src/test/vsrc/fpga_sim/xdma_axi.v-1
- src/test/vsrc/fpga_sim/xdma_clock.v-1
- src/test/vsrc/fpga_sim/xdma_wrapper.v+10-24
- src/test/vsrc/vcs/top.v+17-6
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