fix(difftest): add masked RefillEvent, disable for now

After #3051, we have supported low-power read (read only 5 out of 8
8B-banks) in ICacheDataArray, and in V3, it was further modified to
dynamically compute the mask based on the taken branch location.

Though, previous DiffRefillEvent does not support masked comparison,
instead it checks entire 512bit, so it will fail if we enable checks on
cacheid >=3 (OpenXiangShan/difftest#712). As we're refactoring ICache
recently, we need this check to ensure the refactored code is working
properly.

This commit removes unused idtfr and introduces masked refill-check
for Difftest, where each mask bit controls comparison of 8B data.

However, as the newly added masked Refill fails CI, we disable it for
now, and wait for later fixup.

Co-authored-by: ngc7331 <[email protected]>

Author: klin02

src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala

@@ -1297,7 +1297,7 @@ class MissQueue(edge: TLEdgeOut, reqNum: Int)(implicit p: Parameters) extends DC
     difftest.valid := io.refill_to_ldq.valid && io.refill_to_ldq.bits.hasdata && io.refill_to_ldq.bits.refill_done
     difftest.addr := io.refill_to_ldq.bits.addr
     difftest.data := io.refill_to_ldq.bits.data_raw.asTypeOf(difftest.data)
-    difftest.idtfr := DontCare
+    difftest.mask := VecInit.fill(difftest.mask.getWidth)(true.B).asUInt
   }
 
   // Perf count

src/main/scala/xiangshan/cache/mmu/L2TLB.scala

@@ -553,7 +553,7 @@ class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) wi
     difftest.valid := cache.io.refill.valid
     difftest.addr := difftest_ptw_addr(RegEnable(mem.d.bits.source, mem.d.valid))
     difftest.data := refill_data.asTypeOf(difftest.data)
-    difftest.idtfr := DontCare
+    difftest.mask := VecInit.fill(difftest.mask.getWidth)(true.B).asUInt
   }
 
   if (env.EnableDifftest) {

src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala

@@ -643,29 +643,28 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule with HasICache
     ******************************************************************************
     */
   if (env.EnableDifftest) {
-    val discards = (0 until PortNumber).map { i =>
-      ExceptionType.hasException(toIFU.bits.exception(i)) ||
-      toIFU.bits.pmp_mmio(i) ||
-      Pbmt.isUncache(toIFU.bits.itlb_pbmt(i))
-    }
-    val blkPaddrAll = s2_req_paddr.map(addr => (addr(PAddrBits - 1, blockOffBits) << blockOffBits).asUInt)
-    (0 until ICacheDataBanks).foreach { i =>
-      val diffMainPipeOut = DifftestModule(new DiffRefillEvent, dontCare = true)
-      diffMainPipeOut.coreid := io.hartId
-      diffMainPipeOut.index  := (3 + i).U
-
-      val bankSel = getBankSel(s2_req_offset, s2_valid).reduce(_ | _)
-      val lineSel = getLineSel(s2_req_offset)
-
-      diffMainPipeOut.valid := s2_fire && bankSel(i).asBool && Mux(lineSel(i), !discards(1), !discards(0))
-      diffMainPipeOut.addr := Mux(
-        lineSel(i),
-        blkPaddrAll(1) + (i.U << log2Ceil(blockBytes / ICacheDataBanks)).asUInt,
-        blkPaddrAll(0) + (i.U << log2Ceil(blockBytes / ICacheDataBanks)).asUInt
-      )
-
-      diffMainPipeOut.data  := s2_datas(i).asTypeOf(diffMainPipeOut.data)
-      diffMainPipeOut.idtfr := DontCare
+    val bankSel = getBankSel(s2_req_offset, s2_valid)
+
+    // do difftest for each fetched cache line
+    s2_req_paddr.zipWithIndex.foreach { case (pa, i) =>
+      val difftest = DifftestModule(new DiffRefillEvent, dontCare = true)
+      difftest.coreid := io.hartId
+      difftest.index  := (3 + i).U // magic number 3/4: ICache MainPipe refill test
+
+      difftest.valid := false.B
+//      difftest.valid := s2_fire && !(
+//        ExceptionType.hasException(toIFU.bits.exception(i)) ||
+//          toIFU.bits.pmp_mmio(i) ||
+//          Pbmt.isUncache(toIFU.bits.itlb_pbmt(i))
+//      )
+      difftest.addr := Cat(pa(PAddrBits - 1, blockOffBits), 0.U(blockOffBits.W))
+      difftest.data := s2_datas.asTypeOf(difftest.data)
+      // NOTE: each mask bit controls (512bit / difftest.mask.getWidth) (currently 64bit) comparison
+      // this only works for DataBanks <= difftest.mask.getWidth (and isPow2)
+      difftest.mask := VecInit((0 until difftest.mask.getWidth).map { j =>
+        // the j-th mask locates in (j / (difftest.mask.getWidth / DataBanks)) bank
+        bankSel(i)(j / (difftest.mask.getWidth / ICacheDataBanks))
+      }).asUInt
     }
   }
 }

src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala

@@ -476,6 +476,6 @@ class ICacheMissUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheModu
     difftest.valid  := write_sram_valid
     difftest.addr   := Cat(mshr_resp.blkPaddr, 0.U(blockOffBits.W))
     difftest.data   := respDataReg.asTypeOf(difftest.data)
-    difftest.idtfr  := DontCare
+    difftest.mask   := VecInit.fill(difftest.mask.getWidth)(true.B).asUInt
   }
 }