feat(difftest): support DiffPhyRegState and DiffArchRenameTable (#714)

This commit introduces DiffPhyRegState and DiffArchRenameTable as new Difftest
interfaces. A new option softArchUpdate is also added (disabled by default).

By default, Difftest replaces PhyReg and RenameTable with ArchReg and CommitData
(WriteBack results) on the hardware side to keep backward compatibility.
When softArchUpdate is enabled, this substitution is deferred to the software side,
reducing hardware area overhead by avoiding extra read ports in the register files.

Also we clarify `get_commit_data()` func to `get_int_data()` and `get_fp_data()` for
better readability.

Author: klin02

src/main/scala/Bundles.scala

@@ -175,6 +175,14 @@ class TriggerCSRState extends DifftestBaseBundle {
   val tinfo = UInt(64.W)
 }
 
+class ArchRenameTable(numRegs: Int, numPhyRegs: Int) extends DifftestBaseBundle {
+  val value = Vec(numRegs, UInt(log2Ceil(numPhyRegs).W))
+}
+
+class PhyRegState(numPhyRegs: Int) extends DifftestBaseBundle {
+  val value = Vec(numPhyRegs, UInt(64.W))
+}
+
 class DataWriteback(val numElements: Int) extends DifftestBaseBundle with HasValid with HasAddress {
   val data = UInt(64.W)
 }
@@ -183,36 +191,36 @@ class VecDataWriteback(val numElements: Int) extends DifftestBaseBundle with Has
   val data = Vec(2, UInt(64.W))
 }
 
-class ArchIntRegState extends DifftestBaseBundle {
-  val value = Vec(32, UInt(64.W))
+class ArchRegState(numRegs: Int) extends DifftestBaseBundle {
+  val value = Vec(numRegs, UInt(64.W))
 
-  def apply(i: UInt): UInt = value(i(4, 0))
+  def apply(i: UInt): UInt = value(i(log2Ceil(numRegs), 0))
   def apply(i: Int): UInt = value(i)
-
   def toSeq: Seq[UInt] = value
-  def names: Seq[String] = Seq(
-    "$0", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2",
-    "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
-  )
 
-  def ===(that: ArchIntRegState): Bool = {
+  def ===(that: ArchRegState): Bool = {
     VecInit(value.zip(that.value).map(v => v._1 === v._2)).asUInt.andR
   }
-  def =/=(that: ArchIntRegState): Bool = {
+  def =/=(that: ArchRegState): Bool = {
     VecInit(value.zip(that.value).map(v => v._1 =/= v._2)).asUInt.orR
   }
 }
 
+class ArchIntRegState extends ArchRegState(32) {
+  def names: Seq[String] = Seq(
+    "$0", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2",
+    "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
+  )
+}
+
 class ArchFpRegState extends ArchIntRegState {
   override def names: Seq[String] = Seq(
     "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
     "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",
   )
 }
 
-class ArchVecRegState extends DifftestBaseBundle {
-  val value = Vec(64, UInt(64.W))
-}
+class ArchVecRegState extends ArchRegState(64)
 
 class ArchDelayedUpdate(val numElements: Int) extends DifftestBaseBundle with HasValid with HasAddress {
   val data = UInt(64.W)

src/main/scala/Difftest.scala

@@ -351,7 +351,7 @@ class DiffArchFpDelayedUpdate extends DiffArchDelayedUpdate(32) {
   override val desiredCppName: String = "regs_fp_delayed"
 }
 
-class DiffArchFpRegState extends ArchIntRegState with DifftestBundle {
+class DiffArchFpRegState extends DiffArchIntRegState {
   override val desiredCppName: String = "regs_fp"
   override val desiredOffset: Int = 2
   override val updateDependency: Seq[String] = Seq("commit", "event")
@@ -365,6 +365,43 @@ class DiffArchVecRegState extends ArchVecRegState with DifftestBundle {
   override val supportsDelta: Boolean = true
 }
 
+abstract class DiffArchRenameTable(numRegs: Int, val numPhyRegs: Int)
+  extends ArchRenameTable(numRegs, numPhyRegs)
+  with DifftestBundle {
+  override val updateDependency: Seq[String] = Seq("commit", "event")
+  override val supportsDelta: Boolean = true
+  override def classArgs: Map[String, Any] = Map("numPhyRegs" -> numPhyRegs)
+}
+
+class DiffArchIntRenameTable(numPhyRegs: Int) extends DiffArchRenameTable(32, numPhyRegs) {
+  override val desiredCppName: String = "rat_int"
+}
+
+class DiffArchFpRenameTable(numPhyRegs: Int) extends DiffArchRenameTable(32, numPhyRegs) {
+  override val desiredCppName: String = "rat_fp"
+}
+
+class DiffArchVecRenameTable(numPhyRegs: Int) extends DiffArchRenameTable(64, numPhyRegs) {
+  override val desiredCppName: String = "rat_vec"
+}
+
+abstract class DiffPhyRegState(val numPhyRegs: Int) extends PhyRegState(numPhyRegs) with DifftestBundle {
+  override val supportsDelta: Boolean = true
+  override def classArgs: Map[String, Any] = Map("numPhyRegs" -> numPhyRegs)
+}
+
+class DiffPhyIntRegState(numPhyRegs: Int) extends DiffPhyRegState(numPhyRegs) {
+  override val desiredCppName: String = "pregs_int"
+}
+
+class DiffPhyFpRegState(numPhyRegs: Int) extends DiffPhyRegState(numPhyRegs) {
+  override val desiredCppName: String = "pregs_fp"
+}
+
+class DiffPhyVecRegState(numPhyRegs: Int) extends DiffPhyRegState(numPhyRegs) {
+  override val desiredCppName: String = "pregs_vec"
+}
+
 class DiffVecCSRState extends VecCSRState with DifftestBundle {
   override val desiredCppName: String = "vcsr"
   override val desiredOffset: Int = 5

src/main/scala/Gateway.scala

@@ -47,6 +47,7 @@ case class GatewayConfig(
   traceDump: Boolean = false,
   traceLoad: Boolean = false,
   hierarchicalWiring: Boolean = false,
+  softArchUpdate: Boolean = false,
   isFPGA: Boolean = false,
   isGSIM: Boolean = false,
 ) {
@@ -62,8 +63,8 @@ case class GatewayConfig(
   def hasDeferredResult: Boolean = isNonBlock || hasInternalStep
   def needTraceInfo: Boolean = hasReplay
   def needEndpoint: Boolean =
-    hasGlobalEnable || hasDutZone || isBatch || isSquash || hierarchicalWiring || traceDump || traceLoad
-  def needPreprocess: Boolean = hasDutZone || isBatch || isSquash || needTraceInfo
+    hasGlobalEnable || hasDutZone || isBatch || isSquash || hierarchicalWiring || traceDump || traceLoad || needPreprocess
+  def needPreprocess: Boolean = hasDutZone || isBatch || isSquash || needTraceInfo || !softArchUpdate
   def useDPICtype: Boolean = !isFPGA && !isGSIM
   // Macros Generation for Cpp and Verilog
   def cppMacros: Seq[String] = {
@@ -161,6 +162,7 @@ object Gateway {
       case 'H' => config = config.copy(hierarchicalWiring = true)
       case 'F' => config = config.copy(isFPGA = true)
       case 'G' => config = config.copy(isGSIM = true)
+      case 'U' => config = config.copy(softArchUpdate = true)
       case x   => println(s"Unknown Gateway Config $x")
     }
     config.check()
@@ -182,6 +184,15 @@ object Gateway {
     bundle
   }
 
+  def getInstance(bundles: Seq[DifftestBundle]): Seq[DifftestBundle] = {
+    val archRegs = if (!bundles.exists(_.desiredCppName == "regs_int")) {
+      Preprocess.getArchRegs(bundles, false)
+    } else {
+      Seq.empty
+    }
+    bundles ++ archRegs
+  }
+
   def collect(): GatewayResult = {
     val instances = instanceWithDelay.map(_._1).toSeq
     val sink = if (config.needEndpoint) {
@@ -197,14 +208,14 @@ object Gateway {
       val endpoint = Module(new GatewayEndpoint(instanceWithDelay.toSeq, config))
       endpoint.in := gatewayIn
       GatewayResult(
-        instances = endpoint.instances,
+        instances = getInstance(endpoint.instances),
         structPacked = Some(config.isBatch),
         structAligned = Some(config.isDelta),
         step = Some(endpoint.step),
         fpgaIO = endpoint.fpgaIO,
       )
     } else {
-      GatewayResult(instances = instances) + GatewaySink.collect(config)
+      GatewayResult(instances = getInstance(instances)) + GatewaySink.collect(config)
     }
     sink + GatewayResult(
       cppMacros = config.cppMacros,
@@ -229,7 +240,7 @@ class GatewayEndpoint(instanceWithDelay: Seq[(DifftestBundle, Int)], config: Gat
   }
 
   val preprocessed = if (config.needPreprocess) {
-    WireInit(Preprocess(bundle))
+    WireInit(Preprocess(bundle, config))
   } else {
     WireInit(bundle)
   }