Preprocess: fix VecCommitData index and add numPregs check

Author: klin02

src/main/scala/Bundles.scala

@@ -175,12 +175,12 @@ class TriggerCSRState extends DifftestBaseBundle {
   val tinfo = UInt(64.W)
 }
 
-class ArchRenameTable(numRegs: Int, pregIdxWidth: Int) extends DifftestBaseBundle {
-  val value = Vec(numRegs, UInt(pregIdxWidth.W))
+class ArchRenameTable(numRegs: Int, numPregs: Int) extends DifftestBaseBundle {
+  val value = Vec(numRegs, UInt(log2Ceil(numPregs).W))
 }
 
-class PhyRegState(numRegs: Int) extends DifftestBaseBundle {
-  val value = Vec(numRegs, UInt(64.W))
+class PhyRegState(numPregs: Int) extends DifftestBaseBundle {
+  val value = Vec(numPregs, UInt(64.W))
 }
 
 class DataWriteback(val numElements: Int) extends DifftestBaseBundle with HasValid with HasAddress {
@@ -194,7 +194,7 @@ class VecDataWriteback(val numElements: Int) extends DifftestBaseBundle with Has
 class ArchRegState(numRegs: Int) extends DifftestBaseBundle {
   val value = Vec(numRegs, UInt(64.W))
 
-  def apply(i: UInt): UInt = value(i(log2Ceil(numRegs + 1), 0))
+  def apply(i: UInt): UInt = value(i(log2Ceil(numRegs), 0))
   def apply(i: Int): UInt = value(i)
   def toSeq: Seq[UInt] = value
 

src/main/scala/Difftest.scala

@@ -365,34 +365,40 @@ class DiffArchVecRegState extends ArchVecRegState with DifftestBundle {
   override val supportsDelta: Boolean = true
 }
 
-abstract class DiffArchRenameTable(numRegs: Int, pregIdxWidth: Int)
-  extends ArchRenameTable(numRegs, pregIdxWidth)
+abstract class DiffArchRenameTable(numRegs: Int, val numPregs: Int)
+  extends ArchRenameTable(numRegs, numPregs)
   with DifftestBundle {
   override val updateDependency: Seq[String] = Seq("commit", "event")
   override val supportsDelta: Boolean = true
-  override def classArgs: Map[String, Any] = Map("pregIdxWidth" -> pregIdxWidth)
+  override def classArgs: Map[String, Any] = Map("numPregs" -> numPregs)
 }
-class DiffArchIntRenameTable(pregIdxWidth: Int) extends DiffArchRenameTable(32, pregIdxWidth) {
+
+class DiffArchIntRenameTable(numPregs: Int) extends DiffArchRenameTable(32, numPregs) {
   override val desiredCppName: String = "rat_int"
 }
-class DiffArchFpRenameTable(pregIdxWidth: Int) extends DiffArchRenameTable(32, pregIdxWidth) {
+
+class DiffArchFpRenameTable(numPregs: Int) extends DiffArchRenameTable(32, numPregs) {
   override val desiredCppName: String = "rat_fp"
 }
-class DiffArchVecRenameTable(pregIdxWidth: Int) extends DiffArchRenameTable(64, pregIdxWidth) {
+
+class DiffArchVecRenameTable(numPregs: Int) extends DiffArchRenameTable(64, numPregs) {
   override val desiredCppName: String = "rat_vec"
 }
 
-abstract class DiffPhyRegState(numRegs: Int) extends PhyRegState(numRegs) with DifftestBundle {
+abstract class DiffPhyRegState(val numPregs: Int) extends PhyRegState(numPregs) with DifftestBundle {
   override val supportsDelta: Boolean = true
-  override def classArgs: Map[String, Any] = Map("numRegs" -> numRegs)
+  override def classArgs: Map[String, Any] = Map("numPregs" -> numPregs)
 }
-class DiffPhyIntRegState(numRegs: Int) extends DiffPhyRegState(numRegs) {
+
+class DiffPhyIntRegState(numPregs: Int) extends DiffPhyRegState(numPregs) {
   override val desiredCppName: String = "pregs_int"
 }
-class DiffPhyFpRegState(numRegs: Int) extends DiffPhyRegState(numRegs) {
+
+class DiffPhyFpRegState(numPregs: Int) extends DiffPhyRegState(numPregs) {
   override val desiredCppName: String = "pregs_fp"
 }
-class DiffPhyVecRegState(numRegs: Int) extends DiffPhyRegState(numRegs) {
+
+class DiffPhyVecRegState(numPregs: Int) extends DiffPhyRegState(numPregs) {
   override val desiredCppName: String = "pregs_vec"
 }
 

src/main/scala/Gateway.scala

@@ -185,7 +185,12 @@ object Gateway {
   }
 
   def getInstance(bundles: Seq[DifftestBundle]): Seq[DifftestBundle] = {
-    bundles ++ Preprocess.getArchRegs(bundles, false)
+    val archRegs = if (!bundles.exists(_.desiredCppName == "regs_int")) {
+      Preprocess.getArchRegs(bundles, false)
+    } else {
+      Seq.empty
+    }
+    bundles ++ archRegs
   }
 
   def collect(): GatewayResult = {

src/main/scala/Preprocess.scala

@@ -32,18 +32,31 @@ object Preprocess {
     Seq(("int", new DiffArchIntRegState), ("fp", new DiffArchFpRegState), ("vec", new DiffArchVecRegState)).flatMap {
       case (suffix, gen) =>
         val pregs = bundles.filter(_.desiredCppName == "pregs_" + suffix).asInstanceOf[Seq[DiffPhyRegState]]
-        val rats = bundles.filter(_.desiredCppName == "rat_" + suffix).asInstanceOf[Seq[DiffArchRenameTable]]
-        pregs.zip(rats).map { case (preg, rat) =>
+        if (pregs.nonEmpty) {
+          require(!bundles.exists(_.desiredCppName == "regs_" + suffix))
           if (isHardware) {
-            val archReg = Wire(gen)
-            archReg.coreid := preg.coreid
-            archReg.value.zipWithIndex.foreach { case (data, idx) =>
-              data := preg.value(rat.value(idx))
+            val needRat = pregs.head.numPregs != gen.value.size
+            val rats = bundles.filter(_.desiredCppName == "rat_" + suffix).asInstanceOf[Seq[DiffArchRenameTable]]
+            if (needRat) require(rats.length == pregs.length)
+            pregs.zipWithIndex.map { case (preg, idx) =>
+              val archReg = Wire(gen)
+              archReg.coreid := preg.coreid
+              if (needRat) {
+                val rat = rats(idx)
+                require(rat.numPregs == preg.numPregs)
+                archReg.value.zipWithIndex.foreach { case (data, vid) =>
+                  data := preg.value(rat.value(vid))
+                }
+              } else {
+                archReg.value := preg.value
+              }
+              archReg
             }
-            archReg
           } else {
-            gen
+            Seq.fill(pregs.length)(gen)
           }
+        } else {
+          Seq.empty
         }
     }
   }
@@ -74,7 +87,10 @@ object Preprocess {
         gen.coreid := c.coreid
         gen.index := c.index
         gen.valid := c.valid && (c.v0wen || c.vecwen)
-        gen.data := VecInit(c.otherwpdest.map { wpdest => vreg(wpdest) })
+        gen.data := VecInit(c.otherwpdest.flatMap { wpdest =>
+          val splitDest = (wpdest << 1).asUInt
+          Seq(vreg(splitDest), vreg(splitDest + 1))
+        })
         gen
       }
       Seq(cd) ++ vcd.toSeq
@@ -87,8 +103,8 @@ object Preprocess {
 class PreprocessEndpoint(bundles: Seq[DifftestBundle], config: GatewayConfig) extends Module {
   val in = IO(Input(MixedVec(bundles)))
 
-  def hasBundle(name: String): Boolean = in.exists(_.desiredCppName == name)
-  val replaceReg = if (!config.lazyArchUpdate && hasBundle("pregs_int")) { // extract ArchReg in Hardware
+  val replaceReg = if (!config.lazyArchUpdate && in.exists(_.desiredCppName == "pregs_int")) {
+    // extract ArchReg in Hardware
     Preprocess.replaceRegs(in)
   } else {
     in