diff --git a/src/main/scala/Difftest.scala b/src/main/scala/Difftest.scala
index cdc3274b1..9b953eca3 100644
--- a/src/main/scala/Difftest.scala
+++ b/src/main/scala/Difftest.scala
@@ -572,7 +572,7 @@ object DifftestModule {
     gateway
   }
 
-  def top[T <: Module with HasDiffTestInterfaces](cpuGen: => T): SimTop[T] = new SimTop(cpuGen)
+  def top[T <: RawModule with HasDiffTestInterfaces](cpuGen: => T): SimTop[T] = new SimTop(cpuGen)
 
   def generateSvhInterface(instances: Seq[DifftestBundle], numCores: Int): Unit = {
     // generate interface by jsonProfile, single-core interface will be copied numCore times
diff --git a/src/main/scala/SimTop.scala b/src/main/scala/SimTop.scala
index 103ffb310..1766bb6f9 100644
--- a/src/main/scala/SimTop.scala
+++ b/src/main/scala/SimTop.scala
@@ -61,11 +61,11 @@ class UARTIO extends Bundle {
 trait HasDiffTestInterfaces {
   def cpuName: Option[String] = None
 
-  def connectTopIOs(difftest: DifftestTopIO): Unit = {}
+  def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = Seq.empty
 }
 
 // Top-level module for DiffTest simulation. Will be created by DifftestModule.top
-class SimTop[T <: Module with HasDiffTestInterfaces](cpuGen: => T) extends Module {
+class SimTop[T <: RawModule with HasDiffTestInterfaces](cpuGen: => T) extends Module {
   val cpu = Module(cpuGen)
 
   val cpuName = cpu.cpuName.getOrElse(cpu.getClass.getName.split("\\.").last)
@@ -102,7 +102,11 @@ class SimTop[T <: Module with HasDiffTestInterfaces](cpuGen: => T) extends Modul
     }
   }
 
-  cpu.connectTopIOs(difftest)
+  val cpuIO = cpu.connectTopIOs(difftest)
+  cpuIO.foreach { gen =>
+    val io = IO(chiselTypeOf(gen)).suggestName(gen.instanceName)
+    io <> gen
+  }
 
   // There should not be anymore IOs
   require(DifftestWiring.isEmpty, s"pending wires left: ${DifftestWiring.getPending}")