fix(sstc): do not generate intr when writing CSR stimecmp

In Difftest, all time interrupts should be generated by DUT and be passed to REF. REF should never generate any time interrupts.

In Spike, time interrupts are generated in the following places: (It's easy to find them thorugh mip->backdoor_write_with_mask())

1. In clint.cc, function clint_t::tick().
2. In csrs.cc, function time_counter_csr_t::sync(), which is called by 1.
3. In csrs.cc, function stimecmp_csr_t::unlogged_write

As we disabled clint in spike-difftest, 1 and 2 will never be used. However, 3 is still working and causes some problem. This patch wraps 3 with #ifndef DIFFTEST to disable it.

Author: cebarobot

riscv/csrs.cc

@@ -1761,8 +1761,11 @@ stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const
 }
 
 bool stimecmp_csr_t::unlogged_write(const reg_t val) noexcept {
+  // When difftesting, ref should never generate any time interrupt.
+#ifndef DIFFTEST
   const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0);
   state->mip->backdoor_write_with_mask(mask, state->time->read() >= val ? intr_mask : 0);
+#endif // DIFFTEST
   return basic_csr_t::unlogged_write(val);
 }