Add support for RISC-V vector extension difftest (#3)

Author: weidingliu

difftest/difftest-def.h

@@ -15,6 +15,7 @@
 
 #if defined(CPU_XIANGSHAN)
 #define CONFIG_DIFF_DEBUG_MODE
+// #define CONFIG_DIFF_RVV  // Default off
 #endif
 
 #if defined(CPU_NUTSHELL)
@@ -24,7 +25,11 @@
 #define CONFIG_FLASH_SIZE      0x1000UL
 #define CONFIG_PMP_NUM         0
 #elif defined(CPU_XIANGSHAN)
-#define CONFIG_DIFF_ISA_STRING "RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval"
+    #if defined(CONFIG_DIFF_RVV)
+    #define CONFIG_DIFF_ISA_STRING "RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval"
+    #else
+    #define CONFIG_DIFF_ISA_STRING "RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval"
+    #endif // CONFIG_DIFF_RVV
 #define CONFIG_MEMORY_SIZE     (16 * 1024 * 1024 * 1024UL)
 #define CONFIG_FLASH_BASE      0x10000000UL
 #define CONFIG_FLASH_SIZE      0x100000UL

difftest/difftest.cc

@@ -94,6 +94,25 @@ void DifftestRef::get_regs(diff_context_t *ctx) {
   ctx->dscratch0 = state->csrmap[CSR_DSCRATCH0]->read();
   ctx->dscratch1 = state->csrmap[CSR_DSCRATCH1]->read();
 #endif // DIFF_DEBUG_MODE
+
+#ifdef CONFIG_DIFF_RVV
+  auto& vstate = p->VU;
+  /*******************************ONLY FOR VLEN=128,ELEN=64*******************************************/
+  for(int i = 0; i < NVPR; i++){
+    auto vReg_Val0 = vstate.elt<uint64_t>(i, 0,false);
+    auto vReg_Val1 = vstate.elt<uint64_t>(i, 1,false);
+    ctx->vr[i]._64[0] = vReg_Val0;
+    ctx->vr[i]._64[1] = vReg_Val1;
+  }
+  /***************************************************************************************************/
+  ctx->vstart     = vstate.vstart->read();
+  ctx->vxsat      = vstate.vxsat->read();
+  ctx->vxrm       = vstate.vxrm->read();
+  ctx->vcsr       = state->csrmap[CSR_VCSR]->read();
+  ctx->vl         = vstate.vl->read();
+  ctx->vtype      = vstate.vtype->read();
+  ctx->vlenb      = vstate.vlenb;
+#endif // CONFIG_DIFF_RVV
 }
 
 void DifftestRef::set_regs(diff_context_t *ctx, bool on_demand) {
@@ -183,6 +202,45 @@ void DifftestRef::set_regs(diff_context_t *ctx, bool on_demand) {
     state->csrmap[CSR_DSCRATCH1]->write(ctx->dscratch1);
   }
 #endif // DIFF_DEBUG_MODE
+
+#ifdef CONFIG_DIFF_RVV
+  auto& vstate = p->VU;
+  /**********************ONLY FOR VLEN=128,ELEN=64************************************/
+  for (int i = 0; i < NVPR; i++) {
+    auto &vReg_Val0 = p->VU.elt<uint64_t>(i, 0, true);
+    auto &vReg_Val1 = p->VU.elt<uint64_t>(i, 1, true);
+    if (!on_demand || vReg_Val0 != ctx->vr[i]._64[0]) {
+      vReg_Val0 = ctx->vr[i]._64[0];
+    }
+    if(!on_demand || vReg_Val1 != ctx->vr[i]._64[1]){
+      vReg_Val1 = ctx->vr[i]._64[1];
+    }
+  } 
+  /***********************************************************************************/
+  if (!on_demand || vstate.vstart->read() != ctx->vstart) {
+    vstate.vstart->write_raw(ctx->vstart);
+  }
+  /**********************NEED TO ADD WRITE*********************************************/
+  if (!on_demand || vstate.vxsat->read() != ctx->vxsat) {
+    // vstate.vxsat->write(ctx->vxsat);
+  }
+  if (!on_demand || vstate.vxrm->read() != ctx->vxrm) {
+    vstate.vxrm->write_raw(ctx->vxrm);
+  }
+  /******************************Don't need write vcsr**********************************/
+  // if (!on_demand || state->csrmap[CSR_VCSR]->read() !=ctx->vcsr) {
+  //   csrmap[CSR_VCSR]->write(ctx->vcsr);
+  // }
+  if (!on_demand || vstate.vl->read() != ctx->vl) {
+    vstate.vl->write_raw(ctx->vl);
+  }
+  if (!on_demand || vstate.vtype->read() != ctx->vtype) {
+    vstate.vtype->write_raw(ctx->vtype);
+  }
+  if (!on_demand || vstate.vlenb != ctx->vlenb) {
+    vstate.vlenb = ctx->vlenb;
+  }
+#endif // CONFIG_DIFF_RVV
 }
 
 void DifftestRef::memcpy_from_dut(reg_t dest, void* src, size_t n) {

difftest/difftest.h

@@ -19,6 +19,7 @@ enum { DIFFTEST_TO_DUT, DIFFTEST_TO_REF };
 #define DIFFTEST_LOG_FILE nullptr
 #endif
 
+/***************DON'T CHANGE ORDER****************************/
 typedef struct {
   uint64_t gpr[32];
 #ifdef CONFIG_DIFF_FPU
@@ -43,6 +44,29 @@ typedef struct {
   uint64_t mideleg;
   uint64_t medeleg;
   uint64_t pc;
+#ifdef CONFIG_DIFF_RVV
+  #define VLEN 128
+  #define VENUM64 (VLEN/64)
+  #define VENUM32 (VLEN/32)
+  #define VENUM16 (VLEN/16)
+  #define VENUM8  (VLEN/8)
+
+  union {
+    uint64_t _64[VENUM64];
+    uint32_t _32[VENUM32];
+    uint16_t _16[VENUM16];
+    uint8_t  _8[VENUM8];
+  } vr[32];
+
+  uint64_t vstart;
+  uint64_t vxsat;
+  uint64_t vxrm;
+  uint64_t vcsr;
+  uint64_t vl;
+  uint64_t vtype;
+  uint64_t vlenb;
+#endif // CONFIG_DIFF_RVV
+
 #ifdef CONFIG_DIFF_DEBUG_MODE
   uint64_t debugMode;
   uint64_t dcsr;