Update writable mask for misa of XiangShan

poemonsense · poemonsense · commit 80a3c8160f25 · 2023-09-17T15:15:14.000+08:00
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
@@ -656,7 +656,7 @@ misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t ma
                         | (1L << ('C' - 'A'))
                         | (1L << ('V' - 'A'))
                         )
-#elif defined(CPU_NUTSHELL)
+#elif defined(CPU_NUTSHELL) || defined (CPU_XIANGSHAN)
   write_mask(0 // not allowed
 #else
   write_mask(max_isa & (0  // allow MAFDQCHV bits in MISA to be modified

Original file line number	Diff line number	Diff line change
`@@ -656,7 +656,7 @@ misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t ma`
`656`	`656`	`\| (1L << ('C' - 'A'))`
`657`	`657`	`\| (1L << ('V' - 'A'))`
`658`	`658`	`)`
`659`		`-#elif defined(CPU_NUTSHELL)`
	`659`	`+#elif defined(CPU_NUTSHELL) \|\| defined (CPU_XIANGSHAN)`
`660`	`660`	`write_mask(0 // not allowed`
`661`	`661`	`#else`
`662`	`662`	`write_mask(max_isa & (0 // allow MAFDQCHV bits in MISA to be modified`