TokenizerException: Ambiguous syntax detected when using arrays #25
Description
Thank you very much for this project. this looks great so far. But I stumbled upon an error.
Some synthesis tools don't support the direction of array indices very well, but to get that right, we use for example ar(ar'left+i)
Minimal working example:
test.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port (
clk : in std_logic
);
end entity test;
architecture str of test is
type int_vector is array (natural range<>) of integer;
constant numbers : int_vector := (1, 2, 3, 4, 5);
component reg is
generic (
content : integer := 0
);
port (
clk : in std_logic
);
end component reg;
begin -- architecture str
reg_gen : for i in 0 to 3 generate
reg_inst : reg
generic map (
content => numbers(numbers'left+i)
)
port map (
clk => clk);
end generate reg_gen;
end architecture str;test.py
with open("test.vhd") as fd:
content = fd.read()
print(content)
from pyVHDLParser.Token.Parser import Tokenizer
tokenStream = Tokenizer.GetVHDLTokenizer(content)
# get the iterator for that generator
tokenIterator = iter(tokenStream)
firstToken = next(tokenIterator)
try:
while lastToken := next(tokenIterator):
pass
except StopIteration:
pass
print("first token: {token}".format(token=firstToken))
print("last token: {token}".format(token=lastToken))you will geht the following exception for the line content => numbers(numbers'left+i):
TokenizerException: (line: 26, col: 36): Ambiguous syntax detected. buffer: ''l'
I think this is related to issue #18