Problem parsing generics #29
Description
Final generic line is not parsing, but this code compiles in ModelSim.
Command: VHDLParser block-stream file.vhdl
lutsize : positive range 2 to positive'high := 4Error
ERROR: Expected ';' or ':='.
Code snippet example:
entity comparator is
generic(
depth : positive := 3; -- pipeline depth required
data_width : positive := 32; -- data bus width required for data_a and data_b.
-- number of inputs to a LUT in an FPGA, or for an ASIC, how many bits it is
-- reasonable to operate on in a single clock cycle. Can be odd number.
lutsize : positive range 2 to positive'high := 4
);
port(
clk : in std_ulogic;
reset : in std_ulogic;
data_a : in std_ulogic_vector(data_width-1 downto 0);
data_b : in std_ulogic_vector(data_width-1 downto 0);
equal : out std_ulogic
);
end entity;