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Subtype Constraint in Entity Port Causes Error #9

@bpadalino

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@bpadalino

I'd like to help contribute to this project because I find there aren't enough VHDL parsers that are complete and open source, available for use in other projects.

This seems to be as good a place to start as any, so I cloned the repository and quickly found out the subtype constraint on an entity port doesn't pass the blockstreaming with the error ERROR: Expected ';', ':=' or whitespace after subtype indication.

To be clear, this happens whenever the port has a constraint, like a range constraint: s_axis_tdata : in std_logic_vector(31 downto 0);.

There are a lot of constraints which can apply to the subtype. I'm not necessarily worried about capturing them all, but I am interested in parsing out mostly entities and instantiations in code.

If you have a recommendation on where to look in the code to help add the capabilities, and a list of capabilities in order of precedence you want others to handle, I'd like to try to help out.

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