[RISCV] Remove +zfh from shuffle test. NFC

The scalar insert isn't the interesting bit that we're testing, so
remove it to simplify the check prefixes a bit.

Author: lukel97

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-ZVFH
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-ZVFH
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-ZVFHMIN
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-ZVFHMIN
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <4 x half> @shuffle_v4f16(<4 x half> %x, <4 x half> %y) {
 ; CHECK-LABEL: shuffle_v4f16:
@@ -298,33 +298,12 @@ define <4 x half> @vrgather_shuffle_vv_v4f16(<4 x half> %x, <4 x half> %y) {
 }
 
 define <4 x half> @vrgather_shuffle_vx_v4f16_load(ptr %p) {
-; RV32-ZVFH-LABEL: vrgather_shuffle_vx_v4f16_load:
-; RV32-ZVFH:       # %bb.0:
-; RV32-ZVFH-NEXT:    flh fa5, 2(a0)
-; RV32-ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-ZVFH-NEXT:    vfmv.v.f v8, fa5
-; RV32-ZVFH-NEXT:    ret
-;
-; RV64-ZVFH-LABEL: vrgather_shuffle_vx_v4f16_load:
-; RV64-ZVFH:       # %bb.0:
-; RV64-ZVFH-NEXT:    flh fa5, 2(a0)
-; RV64-ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-ZVFH-NEXT:    vfmv.v.f v8, fa5
-; RV64-ZVFH-NEXT:    ret
-;
-; RV32-ZVFHMIN-LABEL: vrgather_shuffle_vx_v4f16_load:
-; RV32-ZVFHMIN:       # %bb.0:
-; RV32-ZVFHMIN-NEXT:    lh a0, 2(a0)
-; RV32-ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-ZVFHMIN-NEXT:    vmv.v.x v8, a0
-; RV32-ZVFHMIN-NEXT:    ret
-;
-; RV64-ZVFHMIN-LABEL: vrgather_shuffle_vx_v4f16_load:
-; RV64-ZVFHMIN:       # %bb.0:
-; RV64-ZVFHMIN-NEXT:    lh a0, 2(a0)
-; RV64-ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-ZVFHMIN-NEXT:    vmv.v.x v8, a0
-; RV64-ZVFHMIN-NEXT:    ret
+; CHECK-LABEL: vrgather_shuffle_vx_v4f16_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lh a0, 2(a0)
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    ret
   %v = load <4 x half>, ptr %p
   %s = shufflevector <4 x half> %v, <4 x half> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   ret <4 x half> %s