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Basic examples
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‎.gitignore‎

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docs/build
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docs/.eggs
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examples/fpga/*/*/*
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!examples/fpga/*/*/build.py
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!examples/fpga/*/*/Makefile
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examples/target/*/*/*
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!examples/target/*/*/io.partial
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!examples/target/*/*/Makefile

‎examples/fpga/Makefile.in‎

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PICKLED_CTX := ctx.pickled
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.PHONY: all clean
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all: $(PICKLED_CTX)
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clean:
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rm -rf $(PICKLED_CTX) rtl syn vpr
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$(PICKLED_CTX): build.py
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python $<

‎examples/fpga/tiny/frac_k6_N2_8x8/Makefile‎

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include ../../Makefile.in

‎examples/fpga/tiny/frac_k6_N2_8x8/build.py‎

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# -*- encoding: ascii -*-
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from prga.api.context import *
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from prga.api.flow import *
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from prga.api.config import *
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def run():
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context = ArchitectureContext('top', 8, 8, BitchainConfigCircuitryDelegate)
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# 1. routing stuff
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clk = context.create_global('clk', is_clock = True, bind_to_position = (0, 1))
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context.create_segment('L1', 12, 1)
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context.create_segment('L2', 4, 2)
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# 2. create IOB
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iob = context.create_io_block('iob')
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while True:
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clkport = iob.create_global(clk)
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outpad = iob.create_input('outpad', 1)
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inpad = iob.create_output('inpad', 1)
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ioinst = iob.instances['io']
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iff = iob.instantiate(context.primitives['flipflop'], 'iff')
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off = iob.instantiate(context.primitives['flipflop'], 'off')
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iob.connect(clkport, iff.pins['clk'])
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iob.connect(ioinst.pins['inpad'], iff.pins['D'])
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iob.connect(iff.pins['Q'], inpad)
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iob.connect(ioinst.pins['inpad'], inpad)
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iob.connect(clkport, off.pins['clk'])
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iob.connect(off.pins['Q'], ioinst.pins['outpad'])
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iob.connect(outpad, ioinst.pins['outpad'])
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iob.connect(outpad, off.pins['D'])
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break
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# 3. create tile
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iotiles = {}
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for orientation in iter(Orientation):
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if orientation.is_auto:
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continue
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iotiles[orientation] = context.create_tile(
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'io_tile_{}'.format(orientation.name), iob, 4, orientation)
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# 5. create CLB
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clb = context.create_logic_block('clb')
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while True:
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clkport = clb.create_global(clk, Orientation.south)
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ceport = clb.create_input('ce', 1, Orientation.south)
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srport = clb.create_input('sr', 1, Orientation.south)
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cin = clb.create_input('cin', 1, Orientation.north)
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for i in range(2):
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inst = clb.instantiate(context.primitives['fraclut6sffc'], 'cluster{}'.format(i))
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clb.connect(clkport, inst.pins['clk'])
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clb.connect(ceport, inst.pins['ce'])
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clb.connect(srport, inst.pins['sr'])
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clb.connect(clb.create_input('ia' + str(i), 6, Orientation.west), inst.pins['ia'])
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clb.connect(clb.create_input('ib' + str(i), 1, Orientation.west), inst.pins['ib'])
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clb.connect(cin, inst.pins['cin'], pack_pattern = 'carrychain')
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cin = inst.pins['cout']
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clb.connect(inst.pins['oa'], clb.create_output('oa' + str(i), 1, Orientation.east))
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clb.connect(inst.pins['ob'], clb.create_output('ob' + str(i), 1, Orientation.east))
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clb.connect(inst.pins['q'], clb.create_output('q' + str(i), 1, Orientation.east))
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clb.connect(cin, clb.create_output('cout', 1, Orientation.south), pack_pattern = 'carrychain')
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break
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# 6. create direct inter-block tunnels
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context.create_direct_tunnel('carrychain', clb.ports['cout'], clb.ports['cin'], (0, 1))
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# 7. create tile
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clbtile = context.create_tile('clb_tile', clb)
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# 8. fill top-level array
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for x in range(8):
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for y in range(8):
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if x == 0:
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if y > 0 and y < 7:
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context.top.instantiate_element(iotiles[Orientation.west], (x, y))
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elif x == 7:
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if y > 0 and y < 7:
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context.top.instantiate_element(iotiles[Orientation.east], (x, y))
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elif y == 0:
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context.top.instantiate_element(iotiles[Orientation.south], (x, y))
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elif y == 7:
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context.top.instantiate_element(iotiles[Orientation.north], (x, y))
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else:
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context.top.instantiate_element(clbtile, (x, y))
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# 9. flow
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flow = Flow((
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CompleteRoutingBox(BlockFCValue(BlockPortFCValue(0.25), BlockPortFCValue(0.5)),
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{'clb': BlockFCValue(BlockPortFCValue(0.25), BlockPortFCValue(0.25),
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{'cin': BlockPortFCValue(0), 'cout': BlockPortFCValue(0)})}),
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CompleteSwitch(),
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CompleteConnection(),
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GenerateVerilog('rtl'),
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InjectBitchainConfigCircuitry(),
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GenerateVPRXML('vpr'),
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CompletePhysical(),
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ZeroingBRAMWriteEnable(),
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ZeroingBlockPins(),
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GenerateYosysResources('syn'),
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))
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# 10. run flow
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flow.run(context)
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# 11. create a pickled version
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context.pickle('ctx.pickled')
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if __name__ == '__main__':
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run()

‎examples/fpga/tiny/frac_k6_N2_mem8K_8x8/Makefile‎

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include ../../Makefile.in

‎examples/fpga/tiny/frac_k6_N2_mem8K_8x8/build.py‎

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# -*- encoding: ascii -*-
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from prga.api.context import *
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from prga.api.flow import *
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from prga.api.config import *
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def run():
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context = ArchitectureContext('top', 8, 8, BitchainConfigCircuitryDelegate)
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# 1. routing stuff
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clk = context.create_global('clk', is_clock = True, bind_to_position = (0, 1))
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context.create_segment('L1', 12, 1)
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context.create_segment('L2', 4, 2)
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# 2. create IOB
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iob = context.create_io_block('iob')
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while True:
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clkport = iob.create_global(clk)
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outpad = iob.create_input('outpad', 1)
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inpad = iob.create_output('inpad', 1)
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ioinst = iob.instances['io']
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iff = iob.instantiate(context.primitives['flipflop'], 'iff')
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off = iob.instantiate(context.primitives['flipflop'], 'off')
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iob.connect(clkport, iff.pins['clk'])
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iob.connect(ioinst.pins['inpad'], iff.pins['D'])
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iob.connect(iff.pins['Q'], inpad)
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iob.connect(ioinst.pins['inpad'], inpad)
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iob.connect(clkport, off.pins['clk'])
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iob.connect(off.pins['Q'], ioinst.pins['outpad'])
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iob.connect(outpad, ioinst.pins['outpad'])
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iob.connect(outpad, off.pins['D'])
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break
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# 3. create tile
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iotiles = {}
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for orientation in iter(Orientation):
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if orientation.is_auto:
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continue
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iotiles[orientation] = context.create_tile(
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'io_tile_{}'.format(orientation.name), iob, 4, orientation)
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# 5. create CLB
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clb = context.create_logic_block('clb')
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while True:
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clkport = clb.create_global(clk, Orientation.south)
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ceport = clb.create_input('ce', 1, Orientation.south)
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srport = clb.create_input('sr', 1, Orientation.south)
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cin = clb.create_input('cin', 1, Orientation.north)
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for i in range(2):
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inst = clb.instantiate(context.primitives['fraclut6sffc'], 'cluster{}'.format(i))
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clb.connect(clkport, inst.pins['clk'])
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clb.connect(ceport, inst.pins['ce'])
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clb.connect(srport, inst.pins['sr'])
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clb.connect(clb.create_input('ia' + str(i), 6, Orientation.west), inst.pins['ia'])
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clb.connect(clb.create_input('ib' + str(i), 1, Orientation.west), inst.pins['ib'])
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clb.connect(cin, inst.pins['cin'], pack_pattern = 'carrychain')
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cin = inst.pins['cout']
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clb.connect(inst.pins['oa'], clb.create_output('oa' + str(i), 1, Orientation.east))
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clb.connect(inst.pins['ob'], clb.create_output('ob' + str(i), 1, Orientation.east))
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clb.connect(inst.pins['q'], clb.create_output('q' + str(i), 1, Orientation.east))
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clb.connect(cin, clb.create_output('cout', 1, Orientation.south), pack_pattern = 'carrychain')
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break
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# 6. create direct inter-block tunnels
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context.create_direct_tunnel('carrychain', clb.ports['cout'], clb.ports['cin'], (0, 1))
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# 7. create tile
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clbtile = context.create_tile('clb_tile', clb)
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# 8. create BRAM
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bram = context.create_logic_block('bram', 1, 2)
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while True:
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clkport = bram.create_global(clk, Orientation.south, position = (0, 0))
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addrport1 = bram.create_input('addr1', 10, Orientation.west, position = (0, 0))
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dinport1 = bram.create_input('data1', 8, Orientation.west, position = (0, 0))
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weport1 = bram.create_input('we1', 1, Orientation.west, position = (0, 0))
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doutport1 = bram.create_output('out1', 8, Orientation.east, position = (0, 0))
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addrport2 = bram.create_input('addr2', 10, Orientation.west, position = (0, 1))
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dinport2 = bram.create_input('data2', 8, Orientation.west, position = (0, 1))
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weport2 = bram.create_input('we2', 1, Orientation.west, position = (0, 1))
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doutport2 = bram.create_output('out2', 8, Orientation.east, position = (0, 1))
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inst = bram.instantiate(context.primitive_library.get_or_create_memory(10, 8,
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dualport = True), 'ram')
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bram.auto_connect(inst)
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break
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# 9. create tile
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bramtile = context.create_tile('bram_tile', bram)
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# 10. fill top-level array
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for x in range(8):
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for y in range(8):
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if x == 0:
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if y > 0 and y < 7:
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context.top.instantiate_element(iotiles[Orientation.west], (x, y))
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elif x == 7:
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if y > 0 and y < 7:
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context.top.instantiate_element(iotiles[Orientation.east], (x, y))
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elif y == 0:
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context.top.instantiate_element(iotiles[Orientation.south], (x, y))
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elif y == 7:
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context.top.instantiate_element(iotiles[Orientation.north], (x, y))
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elif x in (2, 5):
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if y % 2 == 1:
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context.top.instantiate_element(bramtile, (x, y))
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else:
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context.top.instantiate_element(clbtile, (x, y))
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# 11. flow
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flow = Flow((
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CompleteRoutingBox(BlockFCValue(BlockPortFCValue(0.25), BlockPortFCValue(0.5)),
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{'clb': BlockFCValue(BlockPortFCValue(0.25), BlockPortFCValue(0.25),
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{'cin': BlockPortFCValue(0), 'cout': BlockPortFCValue(0)})}),
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CompleteSwitch(),
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CompleteConnection(),
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GenerateVerilog('rtl'),
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InjectBitchainConfigCircuitry(),
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GenerateVPRXML('vpr'),
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CompletePhysical(),
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ZeroingBRAMWriteEnable(),
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ZeroingBlockPins(),
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GenerateYosysResources('syn'),
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))
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# 11. run flow
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flow.run(context)
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# 12. create a pickled version
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context.pickle('ctx.pickled')
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if __name__ == '__main__':
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run()

‎examples/fpga/tiny/k4_N2_8x8/Makefile‎

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include ../../Makefile.in

‎examples/fpga/tiny/k4_N2_8x8/build.py‎

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# -*- encoding: ascii -*-
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from prga.api.context import *
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from prga.api.flow import *
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from prga.api.config import *
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from itertools import product
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def run():
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context = ArchitectureContext('top', 8, 8, BitchainConfigCircuitryDelegate)
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# 1. routing stuff
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clk = context.create_global('clk', is_clock = True, bind_to_position = (0, 1))
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context.create_segment('L1', 12, 1)
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# 2. create IOB
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iob = context.create_io_block('iob')
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while True:
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outpad = iob.create_input('outpad', 1)
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inpad = iob.create_output('inpad', 1)
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ioinst = iob.instances['io']
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iob.connect(ioinst.pins['inpad'], inpad)
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iob.connect(outpad, ioinst.pins['outpad'])
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break
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# 3. create tile
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iotiles = {}
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for orientation in iter(Orientation):
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if orientation.is_auto:
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continue
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iotiles[orientation] = context.create_tile(
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'io_tile_{}'.format(orientation.name), iob, 4, orientation)
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# 4. create cluster
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cluster = context.create_cluster('cluster')
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while True:
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clkport = cluster.create_input('clk', 1)
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inport = cluster.create_input('in', 4)
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outport = cluster.create_output('out', 1)
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lut = cluster.instantiate(context.primitives['lut4'], 'lutinst')
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ff = cluster.instantiate(context.primitives['flipflop'], 'ffinst')
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cluster.connect(inport, lut.pins['in'])
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cluster.connect(lut.pins['out'], outport)
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cluster.connect(clkport, ff.pins['clk'])
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cluster.connect(lut.pins['out'], ff.pins['D'])
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cluster.connect(ff.pins['Q'], outport)
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break
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# 5. create CLB
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clb = context.create_logic_block('clb')
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while True:
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clkport = clb.create_global(clk, Orientation.south)
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inport = clb.create_input('in', 8, Orientation.west)
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outport = clb.create_output('out', 2, Orientation.east)
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for i in range(2):
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clusterinst = clb.instantiate(cluster, 'cluster{}'.format(i))
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clb.connect(inport[i*4:(i+1)*4], clusterinst.pins['in'])
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clb.connect(clkport, clusterinst.pins['clk'])
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clb.connect(clusterinst.pins['out'], outport[i])
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break
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# 6. create tile
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clbtile = context.create_tile('clb_tile', clb)
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# 7. fill top-level array
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for x, y in product(range(8), range(8)):
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if x == 0:
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if y > 0 and y < 7:
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context.top.instantiate_element(iotiles[Orientation.west], (x, y))
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elif x == 7:
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if y > 0 and y < 7:
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context.top.instantiate_element(iotiles[Orientation.east], (x, y))
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elif y == 0:
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context.top.instantiate_element(iotiles[Orientation.south], (x, y))
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elif y == 7:
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context.top.instantiate_element(iotiles[Orientation.north], (x, y))
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else:
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context.top.instantiate_element(clbtile, (x, y))
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# 11. flow
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flow = Flow((
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CompleteRoutingBox(BlockFCValue(BlockPortFCValue(0.25), BlockPortFCValue(0.5))),
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CompleteSwitch(),
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CompleteConnection(),
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GenerateVerilog('rtl'),
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InjectBitchainConfigCircuitry(),
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GenerateVPRXML('vpr'),
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CompletePhysical(),
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ZeroingBlockPins(),
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GenerateYosysResources('syn'),
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))
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# 11. run flow
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flow.run(context)
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# 12. create a pickled version
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context.pickle('ctx.pickled')
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if __name__ == '__main__':
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run()

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