Support inst-same-cost attribute

Support inst-same-cost attribute

Author: qethu

llvm/lib/Target/Mips/Mips.td

@@ -212,6 +212,10 @@ def FeatureStrictAlign
     : SubtargetFeature<"strict-align", "StrictAlign", "true",
                        "Disable unaligned load store for r6">;
 
+def FeatureInstSameCost
+    : SubtargetFeature<"inst-same-cost", "InstSameCost", "true",
+                       "All the instructions have the same cost">;
+
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -1248,6 +1248,14 @@ bool MipsTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
   return Subtarget.hasMips32();
 }
 
+bool MipsTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
+  // When aggressively optimizing for code size, we prefer to use a div
+  // instruction, as it is usually smaller than the alternative sequence.
+  bool OptSize = Attr.hasFnAttr(Attribute::MinSize);
+  bool isInstSameCost = Subtarget.isInstSameCost();
+  return OptSize || isInstSameCost;
+}
+
 bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
   // We can use ANDI+SLTIU as a bit test. Y contains the bit position.
   // For MIPSR2 or later, we may be able to use the `ext` instruction or its'

llvm/lib/Target/Mips/MipsISelLowering.h

@@ -293,6 +293,8 @@ class TargetRegisterClass;
     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
                                            CombineLevel Level) const override;
 
+    bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
+
     /// Return the register type for a given MVT, ensuring vectors are treated
     /// as a series of gpr sized integers.
     MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,

llvm/lib/Target/Mips/MipsSubtarget.cpp

@@ -83,7 +83,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
       AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false),
       UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
       HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
-      UseIndirectJumpsHazard(false), StrictAlign(false),
+      UseIndirectJumpsHazard(false), StrictAlign(false), InstSameCost(false),
       StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),

llvm/lib/Target/Mips/MipsSubtarget.h

@@ -202,6 +202,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
   // Disable unaligned load store for r6.
   bool StrictAlign;
 
+  // All the instructions have the same cost.
+  bool InstSameCost;
+
   /// The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
   Align stackAlignment;
@@ -382,6 +385,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
     return hasMips32r6() && !StrictAlign;
   }
 
+  bool isInstSameCost() const { return InstSameCost; }
+
   // Set helper classes
   void setHelperClassesMips16();
   void setHelperClassesMipsSE();

llvm/test/CodeGen/Mips/inst-same-cost.ll

@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefix=CHECK
+; RUN: llc -mtriple=mips --mcpu=zkm < %s | FileCheck %s -check-prefix=CHECK-CPU
+; RUN: llc -mtriple=mips --mattr=+inst-same-cost < %s | FileCheck %s -check-prefix=CHECK-CPU
+
+define dso_local noundef range(i32 -5554, 5555) i32 @x(i32 noundef signext %a) local_unnamed_addr #0 {
+; CHECK-LABEL: x:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui $1, 12080
+; CHECK-NEXT:    ori $1, $1, 52665
+; CHECK-NEXT:    mult $4, $1
+; CHECK-NEXT:    mfhi $1
+; CHECK-NEXT:    srl $2, $1, 31
+; CHECK-NEXT:    sra $1, $1, 10
+; CHECK-NEXT:    addu $1, $1, $2
+; CHECK-NEXT:    addiu $2, $zero, 5555
+; CHECK-NEXT:    mul $1, $1, $2
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    subu $2, $4, $1
+;
+; CHECK-CPU-LABEL: x:
+; CHECK-CPU:       # %bb.0: # %entry
+; CHECK-CPU-NEXT:    addiu $1, $zero, 5555
+; CHECK-CPU-NEXT:    div $zero, $4, $1
+; CHECK-CPU-NEXT:    teq $1, $zero, 7
+; CHECK-CPU-NEXT:    jr $ra
+; CHECK-CPU-NEXT:    mfhi $2
+entry:
+  %rem = srem i32 %a, 5555
+  ret i32 %rem
+}
+
+define dso_local noundef range(i32 -5554, 5555) i32 @y(i32 noundef signext %a) local_unnamed_addr #1 {
+; CHECK-LABEL: y:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $1, $zero, 5555
+; CHECK-NEXT:    div $zero, $4, $1
+; CHECK-NEXT:    teq $1, $zero, 7
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    mfhi $2
+;
+; CHECK-CPU-LABEL: y:
+; CHECK-CPU:       # %bb.0: # %entry
+; CHECK-CPU-NEXT:    addiu $1, $zero, 5555
+; CHECK-CPU-NEXT:    div $zero, $4, $1
+; CHECK-CPU-NEXT:    teq $1, $zero, 7
+; CHECK-CPU-NEXT:    jr $ra
+; CHECK-CPU-NEXT:    mfhi $2
+entry:
+  %rem = srem i32 %a, 5555
+  ret i32 %rem
+}
+
+define dso_local noundef range(i32 -5554, 5555) i32 @z(i32 noundef signext %a) local_unnamed_addr #2 {
+; CHECK-LABEL: z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $1, $zero, 5555
+; CHECK-NEXT:    div $zero, $4, $1
+; CHECK-NEXT:    teq $1, $zero, 7
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    mfhi $2
+;
+; CHECK-CPU-LABEL: z:
+; CHECK-CPU:       # %bb.0: # %entry
+; CHECK-CPU-NEXT:    addiu $1, $zero, 5555
+; CHECK-CPU-NEXT:    div $zero, $4, $1
+; CHECK-CPU-NEXT:    teq $1, $zero, 7
+; CHECK-CPU-NEXT:    jr $ra
+; CHECK-CPU-NEXT:    mfhi $2
+entry:
+  %rem = srem i32 %a, 5555
+  ret i32 %rem
+}
+
+attributes #0 = { "target-features"="" }
+attributes #1 = { "target-features"="+inst-same-cost" }
+attributes #2 = { "target-cpu"="zkm" }