Skip to content

Commit fec1857

Browse files
qethuqethu
committed
Add zkm CPU
Support inst-same-const attribute Support div/divu/mod/modu from r6
1 parent ed65665 commit fec1857

File tree

11 files changed

+136
-7
lines changed

11 files changed

+136
-7
lines changed

‎clang/lib/Basic/Targets/Mips.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
4747
{"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"},
4848
{"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
4949
{"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
50-
{"octeon"}, {"octeon+"}, {"p5600"}};
50+
{"octeon"}, {"octeon+"}, {"p5600"}, {"zkm"}};
5151

5252
bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
5353
return llvm::is_contained(ValidCPUNames, Name);

‎llvm/lib/Target/Mips/Mips.td‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,17 @@ def FeatureStrictAlign
212212
: SubtargetFeature<"strict-align", "StrictAlign", "true",
213213
"Disable unaligned load store for r6">;
214214

215+
def FeatureInstSameCost
216+
: SubtargetFeature<"inst-same-cost", "InstSameCost", "true",
217+
"All the instructions have the same cost">;
218+
219+
def FeatureDIVr6 : SubtargetFeature<"divr6", "HasDIVr6",
220+
"true", "Support div/divu/mod/modu instruction from MIPS32r6",
221+
[FeatureMips32r2]>;
222+
def FeatureZKM : SubtargetFeature<"zkm", "HasZKM",
223+
"true", "Mips32r2 with ZKM extension Support",
224+
[FeatureMips32r2, FeatureDIVr6]>;
225+
215226
//===----------------------------------------------------------------------===//
216227
// Register File, Calling Conv, Instruction Descriptions
217228
//===----------------------------------------------------------------------===//
@@ -246,6 +257,7 @@ def : Proc<"mips1", [FeatureMips1]>;
246257
def : Proc<"mips2", [FeatureMips2]>;
247258
def : Proc<"mips32", [FeatureMips32]>;
248259
def : Proc<"mips32r2", [FeatureMips32r2]>;
260+
def : Proc<"zkm", [FeatureMips32r2, FeatureInstSameCost, FeatureZKM]>;
249261
def : Proc<"mips32r3", [FeatureMips32r3]>;
250262
def : Proc<"mips32r5", [FeatureMips32r5]>;
251263
def : Proc<"mips32r6", [FeatureMips32r6]>;

‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -921,8 +921,8 @@ def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
921921
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;
922922
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;
923923
let AdditionalPredicates = [NotInMicroMips] in {
924-
def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
925-
def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
924+
def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, INSN_HAS_DIVR6;
925+
def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, INSN_HAS_DIVR6;
926926
}
927927

928928
def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6;
@@ -952,8 +952,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
952952
def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
953953
def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
954954

955-
def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
956-
def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
955+
def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, INSN_HAS_DIVR6;
956+
def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, INSN_HAS_DIVR6;
957957

958958
def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
959959
def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;

‎llvm/lib/Target/Mips/MipsISelLowering.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1248,6 +1248,14 @@ bool MipsTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
12481248
return Subtarget.hasMips32();
12491249
}
12501250

1251+
bool MipsTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
1252+
// When aggressively optimizing for code size, we prefer to use a div
1253+
// instruction, as it is usually smaller than the alternative sequence.
1254+
bool OptSize = Attr.hasFnAttr(Attribute::MinSize);
1255+
bool isInstSameCost = Subtarget.isInstSameCost();
1256+
return OptSize || isInstSameCost;
1257+
}
1258+
12511259
bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
12521260
// We can use ANDI+SLTIU as a bit test. Y contains the bit position.
12531261
// For MIPSR2 or later, we may be able to use the `ext` instruction or its'

‎llvm/lib/Target/Mips/MipsISelLowering.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -293,6 +293,8 @@ class TargetRegisterClass;
293293
bool shouldFoldConstantShiftPairToMask(const SDNode *N,
294294
CombineLevel Level) const override;
295295

296+
bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
297+
296298
/// Return the register type for a given MVT, ensuring vectors are treated
297299
/// as a series of gpr sized integers.
298300
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,

‎llvm/lib/Target/Mips/MipsInstrInfo.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -256,6 +256,8 @@ def HasVirt : Predicate<"Subtarget->hasVirt()">,
256256
AssemblerPredicate<(all_of FeatureVirt)>;
257257
def HasGINV : Predicate<"Subtarget->hasGINV()">,
258258
AssemblerPredicate<(all_of FeatureGINV)>;
259+
def HasDIVr6 : Predicate<"Subtarget->hasDIVr6()">,
260+
AssemblerPredicate<(all_of FeatureDIVr6)>;
259261
// TODO: Add support for FPOpFusion::Standard
260262
def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion =="
261263
" FPOpFusion::Fast">;
@@ -436,6 +438,11 @@ class INSN_MIPS5_32R2_NOT_32R6_64R6 {
436438
list<Predicate> EncodingPredicates = [HasStdEnc];
437439
}
438440

441+
class INSN_HAS_DIVR6 {
442+
list<Predicate> InsnPredicates = [HasDIVr6];
443+
list<Predicate> EncodingPredicates = [HasStdEnc];
444+
}
445+
439446
class ASE_CNMIPS {
440447
list<Predicate> ASEPredicate = [HasCnMips];
441448
}

‎llvm/lib/Target/Mips/MipsSEISelLowering.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -260,6 +260,13 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
260260
setOperationAction(ISD::STORE, MVT::f64, Custom);
261261
}
262262

263+
if (Subtarget.hasDIVr6()) {
264+
setOperationAction(ISD::SDIV, MVT::i32, Legal);
265+
setOperationAction(ISD::UDIV, MVT::i32, Legal);
266+
setOperationAction(ISD::SREM, MVT::i32, Legal);
267+
setOperationAction(ISD::UREM, MVT::i32, Legal);
268+
}
269+
263270
if (Subtarget.hasMips32r6()) {
264271
// MIPS32r6 replaces the accumulator-based multiplies with a three register
265272
// instruction

‎llvm/lib/Target/Mips/MipsScheduleP5600.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ def MipsP5600Model : SchedMachineModel {
2121
InMicroMips, InMips16Mode,
2222
HasCnMips, HasCnMipsP,
2323
HasDSP, HasDSPR2, HasMips3D, HasMT,
24-
HasCRC];
24+
HasCRC, HasDIVr6];
2525
}
2626

2727
let SchedModel = MipsP5600Model in {

‎llvm/lib/Target/Mips/MipsSubtarget.cpp‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,14 +76,15 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
7676
IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false),
7777
IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
7878
IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false),
79+
HasDIVr6(false), HasZKM(false),
7980
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
8081
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
8182
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
8283
HasDSPR2(false), HasDSPR3(false),
8384
AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false),
8485
UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
8586
HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
86-
UseIndirectJumpsHazard(false), StrictAlign(false),
87+
UseIndirectJumpsHazard(false), StrictAlign(false), InstSameCost(false),
8788
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
8889
InstrInfo(
8990
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
@@ -147,13 +148,17 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
147148
if (hasMips32r6()) {
148149
StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
149150

151+
HasDIVr6 = true;
150152
assert(isFP64bit());
151153
assert(isNaN2008());
152154
assert(inAbs2008Mode());
153155
if (hasDSP())
154156
report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
155157
}
156158

159+
if (hasZKM())
160+
HasDIVr6 = true;
161+
157162
if (NoABICalls && TM.isPositionIndependent())
158163
report_fatal_error("position-independent code requires '-mabicalls'");
159164

‎llvm/lib/Target/Mips/MipsSubtarget.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,10 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
115115
// CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
116116
bool HasCnMipsP;
117117

118+
// CPU supports div/divu/mod/modu of MIPSr6.
119+
bool HasDIVr6;
120+
bool HasZKM;
121+
118122
// isLinux - Target system is Linux. Is false we consider ELFOS for now.
119123
bool IsLinux;
120124

@@ -202,6 +206,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
202206
// Disable unaligned load store for r6.
203207
bool StrictAlign;
204208

209+
// All the instructions have the same cost.
210+
bool InstSameCost;
211+
205212
/// The minimum alignment known to hold of the stack frame on
206213
/// entry to the function and which must be maintained by every function.
207214
Align stackAlignment;
@@ -283,6 +290,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
283290

284291
bool hasCnMips() const { return HasCnMips; }
285292
bool hasCnMipsP() const { return HasCnMipsP; }
293+
bool hasDIVr6() const { return HasDIVr6; }
294+
bool hasZKM() const { return HasZKM; }
286295

287296
bool isLittle() const { return IsLittle; }
288297
bool isABICalls() const { return !NoABICalls; }
@@ -382,6 +391,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
382391
return hasMips32r6() && !StrictAlign;
383392
}
384393

394+
bool isInstSameCost() const { return InstSameCost; }
395+
385396
// Set helper classes
386397
void setHelperClassesMips16();
387398
void setHelperClassesMipsSE();

0 commit comments

Comments
 (0)