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cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/arch
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501 Reviewed-on: https://go-review.googlesource.com/c/go/+/701455 Reviewed-by: Cherry Mui <[email protected]> LUCI-TryBot-Result: Go LUCI <[email protected]> Reviewed-by: Keith Randall <[email protected]>
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-144
lines changed

3 files changed

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-144
lines changed

‎src/cmd/asm/internal/arch/arm64.go‎

Lines changed: 0 additions & 143 deletions
Original file line numberDiff line numberDiff line change
@@ -195,149 +195,6 @@ func ARM64RegisterShift(reg, op, count int16) (int64, error) {
195195
return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
196196
}
197197

198-
// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
199-
func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
200-
Rnum := (reg & 31) + int16(num<<5)
201-
if isAmount {
202-
if num < 0 || num > 7 {
203-
return errors.New("index shift amount is out of range")
204-
}
205-
}
206-
if reg <= arm64.REG_R31 && reg >= arm64.REG_R0 {
207-
if !isAmount {
208-
return errors.New("invalid register extension")
209-
}
210-
switch ext {
211-
case "UXTB":
212-
if a.Type == obj.TYPE_MEM {
213-
return errors.New("invalid shift for the register offset addressing mode")
214-
}
215-
a.Reg = arm64.REG_UXTB + Rnum
216-
case "UXTH":
217-
if a.Type == obj.TYPE_MEM {
218-
return errors.New("invalid shift for the register offset addressing mode")
219-
}
220-
a.Reg = arm64.REG_UXTH + Rnum
221-
case "UXTW":
222-
// effective address of memory is a base register value and an offset register value.
223-
if a.Type == obj.TYPE_MEM {
224-
a.Index = arm64.REG_UXTW + Rnum
225-
} else {
226-
a.Reg = arm64.REG_UXTW + Rnum
227-
}
228-
case "UXTX":
229-
if a.Type == obj.TYPE_MEM {
230-
return errors.New("invalid shift for the register offset addressing mode")
231-
}
232-
a.Reg = arm64.REG_UXTX + Rnum
233-
case "SXTB":
234-
if a.Type == obj.TYPE_MEM {
235-
return errors.New("invalid shift for the register offset addressing mode")
236-
}
237-
a.Reg = arm64.REG_SXTB + Rnum
238-
case "SXTH":
239-
if a.Type == obj.TYPE_MEM {
240-
return errors.New("invalid shift for the register offset addressing mode")
241-
}
242-
a.Reg = arm64.REG_SXTH + Rnum
243-
case "SXTW":
244-
if a.Type == obj.TYPE_MEM {
245-
a.Index = arm64.REG_SXTW + Rnum
246-
} else {
247-
a.Reg = arm64.REG_SXTW + Rnum
248-
}
249-
case "SXTX":
250-
if a.Type == obj.TYPE_MEM {
251-
a.Index = arm64.REG_SXTX + Rnum
252-
} else {
253-
a.Reg = arm64.REG_SXTX + Rnum
254-
}
255-
case "LSL":
256-
a.Index = arm64.REG_LSL + Rnum
257-
default:
258-
return errors.New("unsupported general register extension type: " + ext)
259-
260-
}
261-
} else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
262-
switch ext {
263-
case "B8":
264-
if isIndex {
265-
return errors.New("invalid register extension")
266-
}
267-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
268-
case "B16":
269-
if isIndex {
270-
return errors.New("invalid register extension")
271-
}
272-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
273-
case "H4":
274-
if isIndex {
275-
return errors.New("invalid register extension")
276-
}
277-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
278-
case "H8":
279-
if isIndex {
280-
return errors.New("invalid register extension")
281-
}
282-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
283-
case "S2":
284-
if isIndex {
285-
return errors.New("invalid register extension")
286-
}
287-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
288-
case "S4":
289-
if isIndex {
290-
return errors.New("invalid register extension")
291-
}
292-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
293-
case "D1":
294-
if isIndex {
295-
return errors.New("invalid register extension")
296-
}
297-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
298-
case "D2":
299-
if isIndex {
300-
return errors.New("invalid register extension")
301-
}
302-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
303-
case "Q1":
304-
if isIndex {
305-
return errors.New("invalid register extension")
306-
}
307-
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
308-
case "B":
309-
if !isIndex {
310-
return nil
311-
}
312-
a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_B & 15) << 5)
313-
a.Index = num
314-
case "H":
315-
if !isIndex {
316-
return nil
317-
}
318-
a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_H & 15) << 5)
319-
a.Index = num
320-
case "S":
321-
if !isIndex {
322-
return nil
323-
}
324-
a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_S & 15) << 5)
325-
a.Index = num
326-
case "D":
327-
if !isIndex {
328-
return nil
329-
}
330-
a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
331-
a.Index = num
332-
default:
333-
return errors.New("unsupported simd register extension type: " + ext)
334-
}
335-
} else {
336-
return errors.New("invalid register and extension combination")
337-
}
338-
return nil
339-
}
340-
341198
// ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
342199
func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
343200
var curQ, curSize uint16

‎src/cmd/asm/internal/asm/parse.go‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -775,7 +775,7 @@ func (p *Parser) registerExtension(a *obj.Addr, name string, prefix rune) {
775775

776776
switch p.arch.Family {
777777
case sys.ARM64:
778-
err := arch.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex)
778+
err := arm64.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex)
779779
if err != nil {
780780
p.errorf("%v", err)
781781
}

‎src/cmd/internal/obj/arm64/asm7.go‎

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ import (
3434
"cmd/internal/obj"
3535
"cmd/internal/objabi"
3636
"encoding/binary"
37+
"errors"
3738
"fmt"
3839
"log"
3940
"math"
@@ -7855,3 +7856,146 @@ func (c *ctxt7) encRegShiftOrExt(p *obj.Prog, a *obj.Addr, r int16) uint32 {
78557856
func pack(q uint32, arngA, arngB uint8) uint32 {
78567857
return uint32(q)<<16 | uint32(arngA)<<8 | uint32(arngB)
78577858
}
7859+
7860+
// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
7861+
func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
7862+
Rnum := (reg & 31) + int16(num<<5)
7863+
if isAmount {
7864+
if num < 0 || num > 7 {
7865+
return errors.New("index shift amount is out of range")
7866+
}
7867+
}
7868+
if reg <= REG_R31 && reg >= REG_R0 {
7869+
if !isAmount {
7870+
return errors.New("invalid register extension")
7871+
}
7872+
switch ext {
7873+
case "UXTB":
7874+
if a.Type == obj.TYPE_MEM {
7875+
return errors.New("invalid shift for the register offset addressing mode")
7876+
}
7877+
a.Reg = REG_UXTB + Rnum
7878+
case "UXTH":
7879+
if a.Type == obj.TYPE_MEM {
7880+
return errors.New("invalid shift for the register offset addressing mode")
7881+
}
7882+
a.Reg = REG_UXTH + Rnum
7883+
case "UXTW":
7884+
// effective address of memory is a base register value and an offset register value.
7885+
if a.Type == obj.TYPE_MEM {
7886+
a.Index = REG_UXTW + Rnum
7887+
} else {
7888+
a.Reg = REG_UXTW + Rnum
7889+
}
7890+
case "UXTX":
7891+
if a.Type == obj.TYPE_MEM {
7892+
return errors.New("invalid shift for the register offset addressing mode")
7893+
}
7894+
a.Reg = REG_UXTX + Rnum
7895+
case "SXTB":
7896+
if a.Type == obj.TYPE_MEM {
7897+
return errors.New("invalid shift for the register offset addressing mode")
7898+
}
7899+
a.Reg = REG_SXTB + Rnum
7900+
case "SXTH":
7901+
if a.Type == obj.TYPE_MEM {
7902+
return errors.New("invalid shift for the register offset addressing mode")
7903+
}
7904+
a.Reg = REG_SXTH + Rnum
7905+
case "SXTW":
7906+
if a.Type == obj.TYPE_MEM {
7907+
a.Index = REG_SXTW + Rnum
7908+
} else {
7909+
a.Reg = REG_SXTW + Rnum
7910+
}
7911+
case "SXTX":
7912+
if a.Type == obj.TYPE_MEM {
7913+
a.Index = REG_SXTX + Rnum
7914+
} else {
7915+
a.Reg = REG_SXTX + Rnum
7916+
}
7917+
case "LSL":
7918+
a.Index = REG_LSL + Rnum
7919+
default:
7920+
return errors.New("unsupported general register extension type: " + ext)
7921+
7922+
}
7923+
} else if reg <= REG_V31 && reg >= REG_V0 {
7924+
switch ext {
7925+
case "B8":
7926+
if isIndex {
7927+
return errors.New("invalid register extension")
7928+
}
7929+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8B & 15) << 5)
7930+
case "B16":
7931+
if isIndex {
7932+
return errors.New("invalid register extension")
7933+
}
7934+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_16B & 15) << 5)
7935+
case "H4":
7936+
if isIndex {
7937+
return errors.New("invalid register extension")
7938+
}
7939+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4H & 15) << 5)
7940+
case "H8":
7941+
if isIndex {
7942+
return errors.New("invalid register extension")
7943+
}
7944+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8H & 15) << 5)
7945+
case "S2":
7946+
if isIndex {
7947+
return errors.New("invalid register extension")
7948+
}
7949+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2S & 15) << 5)
7950+
case "S4":
7951+
if isIndex {
7952+
return errors.New("invalid register extension")
7953+
}
7954+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4S & 15) << 5)
7955+
case "D1":
7956+
if isIndex {
7957+
return errors.New("invalid register extension")
7958+
}
7959+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1D & 15) << 5)
7960+
case "D2":
7961+
if isIndex {
7962+
return errors.New("invalid register extension")
7963+
}
7964+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2D & 15) << 5)
7965+
case "Q1":
7966+
if isIndex {
7967+
return errors.New("invalid register extension")
7968+
}
7969+
a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1Q & 15) << 5)
7970+
case "B":
7971+
if !isIndex {
7972+
return nil
7973+
}
7974+
a.Reg = REG_ELEM + (reg & 31) + ((ARNG_B & 15) << 5)
7975+
a.Index = num
7976+
case "H":
7977+
if !isIndex {
7978+
return nil
7979+
}
7980+
a.Reg = REG_ELEM + (reg & 31) + ((ARNG_H & 15) << 5)
7981+
a.Index = num
7982+
case "S":
7983+
if !isIndex {
7984+
return nil
7985+
}
7986+
a.Reg = REG_ELEM + (reg & 31) + ((ARNG_S & 15) << 5)
7987+
a.Index = num
7988+
case "D":
7989+
if !isIndex {
7990+
return nil
7991+
}
7992+
a.Reg = REG_ELEM + (reg & 31) + ((ARNG_D & 15) << 5)
7993+
a.Index = num
7994+
default:
7995+
return errors.New("unsupported simd register extension type: " + ext)
7996+
}
7997+
} else {
7998+
return errors.New("invalid register and extension combination")
7999+
}
8000+
return nil
8001+
}

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