cmd/internal/obj/riscv: add support for Zicond instructions

This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ.

Follow-up to CL 631576
Updates golang#75350

Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907
GitHub-Last-Rev: 6539cc8
GitHub-Pull-Request: golang#75408
Reviewed-on: https://go-review.googlesource.com/c/go/+/702677
Reviewed-by: Mark Freeman <[email protected]>
Reviewed-by: Joel Sing <[email protected]>
Reviewed-by: Meng Zhuo <[email protected]>
Reviewed-by: Michael Knyszek <[email protected]>
Reviewed-by: Mark Ryan <[email protected]>
TryBot-Bypass: Joel Sing <[email protected]>

Author: lxq015

src/cmd/asm/internal/asm/testdata/riscv64.s

@@ -195,6 +195,12 @@ start:
 	RDTIME		X5				// f32210c0
 	RDINSTRET	X5				// f32220c0
 
+	// 12.3: Integer Conditional Operations (Zicond)
+	CZEROEQZ	X5, X6, X7			// b353530e
+	CZEROEQZ	X5, X7				// b3d3530e
+	CZERONEZ	X5, X6, X7			// b373530e
+	CZERONEZ	X5, X7				// b3f3530e
+
 	// 13.1: Multiplication Operations
 	MUL	X5, X6, X7				// b3035302
 	MULH	X5, X6, X7				// b3135302

src/cmd/internal/obj/riscv/anames.go

@@ -409,6 +409,10 @@ const (
 	ACSRRSI
 	ACSRRCI
 
+	// 12.3: Integer Conditional Operations (Zicond)
+	ACZEROEQZ
+	ACZERONEZ
+
 	// 13.1: Multiplication Operations
 	AMUL
 	AMULH

src/cmd/internal/obj/riscv/cpu.go

@@ -1948,6 +1948,10 @@ var instructions = [ALAST & obj.AMask]instructionData{
 	ACSRRW & obj.AMask:  {enc: iIIEncoding, immForm: ACSRRWI},
 	ACSRRWI & obj.AMask: {enc: iIIEncoding},
 
+	// 12.3: "Zicond" Extension for Integer Conditional Operations
+	ACZERONEZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+	ACZEROEQZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+
 	// 13.1: Multiplication Operations
 	AMUL & obj.AMask:    {enc: rIIIEncoding, ternary: true},
 	AMULH & obj.AMask:   {enc: rIIIEncoding, ternary: true},