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1 | 1 | Introduction |
2 | 2 | ============ |
3 | 3 |
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4 | | -HDL converter (between VHDL, SystemVerilog and/or Verilog), based on `GHDL <https://github.com/ghdl/ghdl>`_, `Yosys <https://github.com/YosysHQ/yosys>`_, `Synlig <https://github.com/chipsalliance/synlig>`_ and the plugins `ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`_ and `yosys-slang <https://github.com/povik/yosys-slang>`_. |
| 4 | +HDL converter provides a set of command-line utilities for converting between VHDL, SystemVerilog, and Verilog. |
| 5 | +Those, gathers files and options, then orchestrates the execution of the following tools - either separately or in combination when required. |
5 | 6 |
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6 | | -It relies on `Docker <https://docs.docker.com/get-docker>`_ and `PyFPGA containers <https://github.com/PyFPGA/containers>`_. |
| 7 | +* `GHDL <https://github.com/ghdl/ghdl>`_ |
| 8 | +* `Yosys <https://github.com/YosysHQ/yosys>`_ |
| 9 | +* `Synlig <https://github.com/chipsalliance/synlig>`_ |
| 10 | +* `ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`_ |
| 11 | +* `yosys-slang <https://github.com/povik/yosys-slang>`_ |
7 | 12 |
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8 | | -* ``vhdl2vhdl``: converts from a newer VHDL to VHDL'93 (using ``ghdl``). |
9 | | -* ``vhdl2vlog``: converts from VHDL to Verilog (backends: ``ghdl`` or ``yosys``). |
10 | | -* ``slog2vlog``: converts from SystemVerilog to Verilog (frontends: ``slang``, ``synlig`` or ``yosys``). |
| 13 | +To avoid the need to install multiple tools, it relies on `Docker <https://docs.docker.com/get-docker>`_ and `PyFPGA containers <https://github.com/PyFPGA/containers>`_. |
| 14 | + |
| 15 | +Command-line utilities |
| 16 | +---------------------- |
| 17 | + |
| 18 | +* ``vhdl2vhdl``: converts from a newer VHDL to VHDL'93. |
| 19 | + * Solved using ``ghdl``. |
| 20 | +* ``vhdl2vlog``: converts from VHDL to Verilog. |
| 21 | + * This has two alternatives: |
| 22 | + * Purely ``ghdl`` (default). |
| 23 | + * ``ghdl-yosys-plugin`` as frontend and ``yosys`` as backend. |
| 24 | +* ``slog2vlog``: converts from SystemVerilog to Verilog. |
| 25 | + * This has three alternatives: |
| 26 | + * ``yosys-slang`` as frontend and ``yosys`` as backend (default). |
| 27 | + * Purely ``synlig`` (based on ``Surelog`` and ``yosys``). |
| 28 | + * Purely ``yosys`` (simpler SV support, but could be sufficient in some cases). |
| 29 | + |
| 30 | +.. note:: |
| 31 | + Multiple alternatives are provided so you can try different options if one does not work. |
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