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PyFPGA/HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

vhdl

verilog

systemverilog

ghdl

yosys

• Python
·
• 25
·
• Updated
  on Mar 5, 2025

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