Improve HDLReader and its test

Author: rodrigomelo9

hdltools/hdl_reader.py

@@ -1,12 +1,12 @@
 #
-# Copyright (C) 2025 HDLtools Project
+# Copyright (C) 2025-2026 HDLtools Project
 #
 # SPDX-License-Identifier: GPL-3.0-or-later
 #
 
 """
-Reads and sanitizes the input HDL code by removing comments, extra whitespaces
-and newlines.
+Reads and sanitizes the input HDL code by removing comments, trailing espaces
+and multiple empty lines.
 """
 
 import re
@@ -27,15 +27,30 @@ def set_code(self, code):
         """Directly sets the HDL code."""
         self.code = code
 
-    def is_vhdl(self):
-        """Return True if the code seems to be VHDL."""
-        return 'endmodule' not in self.code.lower()
-
     def get_code(self):
         """Retrieves the sanitized HDL code."""
-        if self.is_vhdl():
-            text = re.sub(r'--[^\n]*', '', self.code)
+        text = self.code
+        text = re.sub(r'/\*.*?\*/', '', text, flags=re.DOTALL)
+        if self._is_vhdl(text):
+            text = re.sub(r'--.*', '', text)
         else:
-            text = re.sub(r'//[^\n]*', '', self.code)
-            text = re.sub(r'/\*.*?\*/', '', text, flags=re.DOTALL)
-        return re.sub(r'\s+', ' ', text).strip()
+            text = re.sub(r'//.*', '', text)
+        text = re.sub(r'[ \t]+$', '', text, flags=re.MULTILINE)
+        text = re.sub(r'\n{3,}', '\n\n', text)
+        return text.strip()
+
+    def _is_vhdl(self, text):
+        """Heuristic to determine if the code is VHDL or Verilog."""
+        vhdl_score = 0
+        vlog_score = 0
+
+        vhdl_keywords = r'\b(library|entity|architecture|signal|begin)\b'
+        vlog_keywords = r'\b(endmodule|assign|logic|wire|reg|parameter)\b'
+
+        vhdl_matches = re.findall(vhdl_keywords, text, re.IGNORECASE)
+        vhdl_score += len(set(vhdl_matches))
+
+        vlog_matches = re.findall(vlog_keywords, text)
+        vlog_score += len(set(vlog_matches))
+
+        return vhdl_score > vlog_score

tests/test_reader.py

@@ -3,20 +3,89 @@
 from pathlib import Path
 from hdltools.hdl_reader import HDLReader
 
+INPUT = {}
+OUTPUT = {}
 
-@pytest.fixture
-def vcode():
-    vfile = Path(__file__).parent.resolve() / 'hdl' / 'modules.sv'
-    vobj = HDLReader()
-    vobj.read_file(vfile)
-    return vobj.get_code()
+INPUT['vhdl'] = '''
+/*
+  Block comments (added in VHDL 2008)
+*/
+library IEEE; -- aaa
+use IEEE.STD_LOGIC_1164.ALL; -- bbb
+-- ccc
+entity dut is
+  port (
+    data_i :  in std_logic; -- input
+    data_o : out std_logic  -- output
+  );
+end dut;
+-- ddd
+-- eee
+architecture behav of dut /* fff */is
+begin
+/* ggg -- */
+    data_o <= data_i;
+/*
+  hhh
+-- */
+end behav;
+'''
+
+OUTPUT['vhdl'] = '''
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity dut is
+  port (
+    data_i :  in std_logic;
+    data_o : out std_logic
+  );
+end dut;
+
+architecture behav of dut is
+begin
+
+    data_o <= data_i;
 
+end behav;
+'''
 
-def test_comments(vcode):
-    comment_patterns = ['//', '/*', '*/', '--']
-    assert not any(pattern in vcode for pattern in comment_patterns)
+INPUT['vlog'] = '''
+/*
+  Block comments
+*/
+// aaa
+module dut (
+  input  data_i, // input
+  output data_o  // output
+);
+// bbb
+// ccc
+/* ddd // */
+  assign /* eee // */data_o = data_i;
+/*
+  fff
+// */
+endmodule
+'''
 
+OUTPUT['vlog'] = '''
+module dut (
+  input  data_i,
+  output data_o
+);
 
-def test_spaces(vcode):
-    assert '\n' not in vcode
-    assert '  ' not in vcode
+  assign data_o = data_i;
+
+endmodule
+'''
+
+
+@pytest.mark.parametrize("input_code, expected_output", [
+    (INPUT['vhdl'], OUTPUT['vhdl']),
+    (INPUT['vlog'], OUTPUT['vlog']),
+], ids=["VHDL", "Verilog"])
+def test_remove_comments(input_code, expected_output):
+    vobj = HDLReader()
+    vobj.set_code(input_code)
+    assert vobj.get_code() == expected_output.strip()