yosys: added a Verilog example

Author: rodrigomelo9

yosys/Makefile

@@ -0,0 +1,11 @@
+#!/usr/bin/make
+
+DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta
+
+COMMAND=bash
+
+vlog vhdl:
+	$(DOCKER_CMD) $(COMMAND) $@.sh
+
+clean:
+	rm -fr *.cf

yosys/README.md

@@ -0,0 +1,6 @@
+# Notes about Yosys
+
+> Last update: Nov 2021
+
+* Specify a REAL parameter is not supported (`ERROR: Can't decode value '1.1'!`)
+  * As a workaround, I set SKIP_REA

yosys/vlog.sh

@@ -0,0 +1,13 @@
+#!/bin/bash
+
+set -e
+
+yosys -Q -p '
+verilog_defaults -add -I../resources/vlog/path1;
+verilog_defaults -add -I../resources/vlog/path2;
+verilog_defines -DARCH_SEL=1;
+read_verilog -defer ../resources/vlog/blink.v;
+read_verilog -defer ../resources/vlog/top.v;
+chparam -set BOO 1 -set INT 255 -set LOG 1 -set VEC 255 -set CHR "Z" -set STR "WXYZ" -set SKIP_REA 1 Top;
+synth -top Top
+'