examples: added nexys3 (ise)

Author: rodrigomelo9

examples/ise/ise.py

@@ -11,19 +11,30 @@
 parser.add_argument(
     '--action', choices=['generate', 'transfer', 'all'], default='generate',
 )
+parser.add_argument(
+    '--board',
+    choices=['nexys3', 's6micro'],
+    default='nexys3'
+)
 args = parser.parse_args()
 
+BOARDS = {
+    'nexys3': ['XC6SLX16-3-CSG324', 'nexys3.ucf', 'nexys3.xcf'],
+    's6micro': ['XC6SLX9-2-CSG324', 's6micro.ucf', 's6micro.xcf']
+}
+
 prj = Project('ise')
-prj.set_part('XC6SLX9-2-CSG324')
+prj.set_part(BOARDS[args.board][0])
 
-prj.set_outdir('../../build/ise')
+prj.set_outdir('../../build/ise-{}'.format(args.board))
 
 prj.add_files('../../hdl/blinking.vhdl', library='examples')
 prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
 prj.add_files('../../hdl/top.vhdl')
 prj.set_top('Top')
-prj.add_files('s6micro.xcf')
-prj.add_files('s6micro.ucf')
+
+prj.add_files(BOARDS[args.board][1])
+prj.add_files(BOARDS[args.board][2])
 
 if args.action in ['generate', 'all']:
     try:

examples/ise/nexys3.ucf

@@ -0,0 +1,7 @@
+# User Constraints File
+#
+# Used during the implementation to specify timing, placement and pinout
+# constraints.
+
+NET "clk_i" LOC = "V10";
+NET "led_o" LOC = "U16";

examples/ise/nexys3.xcf

@@ -0,0 +1,6 @@
+# Xilinx Constraint File
+#
+# Used during the synthesis (XST) to specify timing and synthesis constraints.
+
+NET "clk_i" TNM_NET = "clk_i";
+TIMESPEC "TS_clk_i" = PERIOD "clk_i" 10.00 ns HIGH 50%;