submodule support child definitions in text format

Author: shtaxxx

tests/core/submodule_/read_verilog/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/core/submodule_/read_verilog/submodule_read_verilog.py

@@ -0,0 +1,77 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+import collections
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+
+verilog_blinkled = """
+module blinkled #
+(
+  parameter WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output reg [WIDTH-1:0] LED,
+  output [WIDTH-1:0] dummy_out0,
+  output [WIDTH-1:0] dummy_out1,
+  output [WIDTH-1:0] dummy_out2,
+  input [WIDTH-1:0] dummy_in0,
+  input [WIDTH-1:0] dummy_in1,
+  input [WIDTH-1:0] dummy_in2
+);
+
+  reg [32-1:0] count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+
+
+endmodule
+"""
+
+
+def mkTop():
+    m = Module('top')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.Output('LED', width)
+
+    sub = Submodule(m, verilog_blinkled, 'inst_blinkled',
+                    arg_params=(('WIDTH', width),),
+                    arg_ports=(('LED', led), ('CLK', clk), ('RST', rst)),
+                    as_io=('dummy_out0', 'dummy_in0'), as_wire=('dummy_out1', 'dummy_in1'))
+
+    return m
+
+if __name__ == '__main__':
+    top = mkTop()
+    verilog = top.to_verilog()
+    print(verilog)

tests/core/submodule_/read_verilog/test_submodule_read_verilog.py

@@ -0,0 +1,103 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import veriloggen
+import submodule_read_verilog
+
+expected_verilog = """
+module top #
+(
+  parameter WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output [WIDTH-1:0] LED,
+  output [WIDTH-1+1-1:0] dummy_out0,
+  input [WIDTH-1+1-1:0] dummy_in0
+);
+
+  wire [WIDTH-1+1-1:0] dummy_out2;
+  reg [WIDTH-1+1-1:0] dummy_in2;
+  wire [WIDTH-1+1-1:0] dummy_out1;
+  wire [WIDTH-1+1-1:0] dummy_in1;
+
+  blinkled
+  #(
+    .WIDTH(WIDTH)
+  )
+  inst_blinkled
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED),
+    .dummy_out0(dummy_out0),
+    .dummy_out1(dummy_out1),
+    .dummy_out2(dummy_out2),
+    .dummy_in0(dummy_in0),
+    .dummy_in1(dummy_in1),
+    .dummy_in2(dummy_in2)
+  );
+
+
+endmodule
+
+
+
+module blinkled #
+(
+  parameter WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output reg [WIDTH-1:0] LED,
+  output [WIDTH-1:0] dummy_out0,
+  output [WIDTH-1:0] dummy_out1,
+  output [WIDTH-1:0] dummy_out2,
+  input [WIDTH-1:0] dummy_in0,
+  input [WIDTH-1:0] dummy_in1,
+  input [WIDTH-1:0] dummy_in2
+);
+
+  reg [32-1:0] count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+
+
+endmodule
+"""
+
+
+def test():
+    test_module = submodule_read_verilog.mkTop()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

veriloggen/core/submodule.py

@@ -3,6 +3,7 @@
 import collections
 import veriloggen.core.module as module
 import veriloggen.core.vtypes as vtypes
+import veriloggen.verilog.from_verilog as from_verilog
 
 
 class Submodule(vtypes.VeriloggenNode):
@@ -11,9 +12,18 @@ class Submodule(vtypes.VeriloggenNode):
     def __init__(self, parent, child,
                  name=None, prefix=None,
                  arg_params=None, arg_ports=None,
-                 as_io=None, as_wire=None):
+                 as_io=None, as_wire=None, topmodule=None):
 
         self.parent = parent
+
+        # child module definition as Verilog HDL source code text
+        if isinstance(child, str):
+            modules = from_verilog.read_verilog_module_str(child)
+            if topmodule is None:
+                child = list(modules.values())[0]
+            else:
+                child = modules[topmodule]
+
         self.child = child
 
         if name is None: