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read_verilog_nested
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‎tests/core/submodule_/read_verilog_nested/Makefile‎

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/core/submodule_/read_verilog_nested/submodule_read_verilog_nested.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import collections
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
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os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
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from veriloggen import *
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verilog_blinkled = """
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module blinkled #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output [WIDTH-1:0] LED,
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output [WIDTH-1:0] dummy_out0,
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output [WIDTH-1:0] dummy_out1,
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output [WIDTH-1:0] dummy_out2,
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input [WIDTH-1:0] dummy_in0,
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input [WIDTH-1:0] dummy_in1,
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input [WIDTH-1:0] dummy_in2
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);
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sub_blinkled
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#(
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.WIDTH(WIDTH)
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)
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inst_sub_blinkled
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(
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.CLK(CLK),
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.RST(RST),
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.LED(LED),
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.dummy_out0(dummy_out0),
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.dummy_out1(dummy_out1),
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.dummy_out2(dummy_out2),
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.dummy_in0(dummy_in0),
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.dummy_in1(dummy_in1),
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.dummy_in2(dummy_in2)
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);
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endmodule
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module sub_blinkled #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output reg [WIDTH-1:0] LED,
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output [WIDTH-1:0] dummy_out0,
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output [WIDTH-1:0] dummy_out1,
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output [WIDTH-1:0] dummy_out2,
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input [WIDTH-1:0] dummy_in0,
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input [WIDTH-1:0] dummy_in1,
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input [WIDTH-1:0] dummy_in2
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);
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reg [32-1:0] count;
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always @(posedge CLK) begin
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if(RST) begin
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count <= 0;
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end else begin
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if(count == 1023) begin
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count <= 0;
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end else begin
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count <= count + 1;
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end
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end
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end
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always @(posedge CLK) begin
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if(RST) begin
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LED <= 0;
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end else begin
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if(count == 1023) begin
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LED <= LED + 1;
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end
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end
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end
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endmodule
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"""
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def mkTop():
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m = Module('top')
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width = m.Parameter('WIDTH', 8)
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clk = m.Input('CLK')
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rst = m.Input('RST')
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led = m.Output('LED', width)
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sub = Submodule(m, verilog_blinkled, 'inst_blinkled',
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arg_params=(('WIDTH', width),),
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arg_ports=(('LED', led), ('CLK', clk), ('RST', rst)),
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as_io=('dummy_out0', 'dummy_in0'), as_wire=('dummy_out1', 'dummy_in1'),
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topmodule='blinkled')
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return m
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if __name__ == '__main__':
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top = mkTop()
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verilog = top.to_verilog()
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print(verilog)

‎tests/core/submodule_/read_verilog_nested/test_submodule_read_verilog_nested.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import veriloggen
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import submodule_read_verilog_nested
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expected_verilog = """
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module top #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output [WIDTH-1:0] LED,
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output [WIDTH-1+1-1:0] dummy_out0,
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input [WIDTH-1+1-1:0] dummy_in0
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);
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wire [WIDTH-1+1-1:0] dummy_out2;
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reg [WIDTH-1+1-1:0] dummy_in2;
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wire [WIDTH-1+1-1:0] dummy_out1;
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wire [WIDTH-1+1-1:0] dummy_in1;
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blinkled
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#(
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.WIDTH(WIDTH)
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)
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inst_blinkled
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(
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.CLK(CLK),
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.RST(RST),
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.LED(LED),
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.dummy_out0(dummy_out0),
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.dummy_out1(dummy_out1),
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.dummy_out2(dummy_out2),
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.dummy_in0(dummy_in0),
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.dummy_in1(dummy_in1),
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.dummy_in2(dummy_in2)
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);
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endmodule
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module blinkled #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output [WIDTH-1:0] LED,
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output [WIDTH-1:0] dummy_out0,
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output [WIDTH-1:0] dummy_out1,
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output [WIDTH-1:0] dummy_out2,
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input [WIDTH-1:0] dummy_in0,
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input [WIDTH-1:0] dummy_in1,
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input [WIDTH-1:0] dummy_in2
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);
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sub_blinkled
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#(
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.WIDTH(WIDTH)
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)
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inst_sub_blinkled
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(
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.CLK(CLK),
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.RST(RST),
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.LED(LED),
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.dummy_out0(dummy_out0),
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.dummy_out1(dummy_out1),
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.dummy_out2(dummy_out2),
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.dummy_in0(dummy_in0),
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.dummy_in1(dummy_in1),
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.dummy_in2(dummy_in2)
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);
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endmodule
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module sub_blinkled #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output reg [WIDTH-1:0] LED,
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output [WIDTH-1:0] dummy_out0,
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output [WIDTH-1:0] dummy_out1,
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output [WIDTH-1:0] dummy_out2,
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input [WIDTH-1:0] dummy_in0,
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input [WIDTH-1:0] dummy_in1,
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input [WIDTH-1:0] dummy_in2
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);
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reg [32-1:0] count;
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always @(posedge CLK) begin
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if(RST) begin
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count <= 0;
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end else begin
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if(count == 1023) begin
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count <= 0;
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end else begin
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count <= count + 1;
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end
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end
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end
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always @(posedge CLK) begin
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if(RST) begin
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LED <= 0;
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end else begin
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if(count == 1023) begin
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LED <= LED + 1;
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end
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end
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end
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endmodule
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"""
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def test():
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test_module = submodule_read_verilog_nested.mkTop()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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parser = VerilogParser()
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expected_ast = parser.parse(expected_verilog)
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == code)

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