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veriloggen/types/axi.py

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Original file line numberDiff line numberDiff line change
@@ -2257,6 +2257,11 @@ def __init__(self, m, name, clk, rst, datawidth=32,
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self.noio = noio
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if not hasattr(self.m, 'streaminbus'):
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self.m.streaminbus = []
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self.m.streaminbus.append(self)
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itype = util.t_Wire if noio else None
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otype = util.t_Wire if noio else None
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@@ -2413,6 +2418,11 @@ def __init__(self, m, name, clk, rst, datawidth=32,
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self.noio = noio
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if not hasattr(self.m, 'streamoutbus'):
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self.m.streamoutbus = []
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self.m.streamoutbus.append(self)
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itype = util.t_Wire if noio else None
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otype = util.t_Reg if noio else None
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