@@ -76,7 +76,7 @@ def name(self, prefix=None):
7676 clsname = self .__class__ .__name__ .lower ()
7777 if prefix is None :
7878 prefix = 'tmp'
79- return '_' .join (['__dataflow ' , clsname , prefix , str (self .object_id )])
79+ return '_' .join (['_dataflow ' , clsname , prefix , str (self .object_id )])
8080
8181
8282class _Numeric (_Node ):
@@ -579,7 +579,6 @@ def _implement(self, m, seq):
579579 width = self .bit_length ()
580580 signed = self .get_signed ()
581581
582- tmp = m .get_tmp ()
583582 data = m .Reg (self .name ('data' ), width , initval = 0 , signed = signed )
584583 valid = m .Reg (self .name ('valid' ), initval = 0 )
585584 ready = m .Wire (self .name ('ready' ))
@@ -649,7 +648,6 @@ def _implement(self, m, seq):
649648 width = self .bit_length ()
650649 signed = self .get_signed ()
651650
652- tmp = m .get_tmp ()
653651 data = m .Reg (self .name ('data' ), width , initval = 0 , signed = signed )
654652 valid = m .Reg (self .name ('valid' ), initval = 0 )
655653 ready = m .Wire (self .name ('ready' ))
@@ -714,7 +712,6 @@ def _implement(self, m, seq):
714712 width = self .bit_length ()
715713 signed = self .get_signed ()
716714
717- tmp = m .get_tmp ()
718715 data = m .Wire (self .name ('data' ), width , signed = signed )
719716 valid = m .Wire (self .name ('valid' ))
720717 ready = m .Wire (self .name ('ready' ))
@@ -815,7 +812,6 @@ def _implement(self, m, seq):
815812 width = self .bit_length ()
816813 signed = self .get_signed ()
817814
818- tmp = m .get_tmp ()
819815 data = m .Wire (self .name ('data' ), width , signed = signed )
820816 valid = m .Wire (self .name ('valid' ))
821817 ready = m .Wire (self .name ('ready' ))
@@ -960,7 +956,6 @@ def _implement(self, m, seq):
960956 width = self .bit_length ()
961957 signed = self .get_signed ()
962958
963- tmp = m .get_tmp ()
964959 data = m .Wire (self .name ('data' ), width , signed = signed )
965960 valid = m .Wire (self .name ('valid' ))
966961 ready = m .Wire (self .name ('ready' ))
@@ -1267,7 +1262,6 @@ def _implement(self, m, seq):
12671262 width = self .bit_length ()
12681263 signed = False
12691264
1270- tmp = m .get_tmp ()
12711265 data = m .Reg (self .name ('data' ), width , initval = 0 , signed = signed )
12721266 valid = m .Reg (self .name ('valid' ), initval = 0 )
12731267 ready = m .Wire (self .name ('ready' ))
@@ -1580,7 +1574,6 @@ def _implement(self, m, seq):
15801574 width = self .bit_length ()
15811575 signed = self .get_signed ()
15821576
1583- tmp = m .get_tmp ()
15841577 data = m .Reg (self .name ('data' ), width , initval = 0 , signed = signed )
15851578 valid = m .Reg (self .name ('valid' ), initval = 0 )
15861579 ready = m .Wire (self .name ('ready' ))
@@ -1894,7 +1887,6 @@ def _implement(self, m, seq):
18941887 width = self .bit_length ()
18951888 signed = self .get_signed ()
18961889
1897- tmp = m .get_tmp ()
18981890 data = m .Wire (self .name ('data' ), width , signed = signed )
18991891 valid = m .Reg (self .name ('valid' ), initval = 0 )
19001892 ready = m .Wire (self .name ('ready' ))
@@ -1966,7 +1958,6 @@ def _implement(self, m, seq):
19661958 width = self .bit_length ()
19671959 signed = self .get_signed ()
19681960
1969- tmp = m .get_tmp ()
19701961 data = m .Reg (self .name ('data' ), width , initval = 0 , signed = signed )
19711962 valid = m .Reg (self .name ('valid' ), initval = 0 )
19721963 ready = m .Wire (self .name ('ready' ))
@@ -2024,7 +2015,6 @@ def _implement(self, m, seq):
20242015 width = self .bit_length ()
20252016 signed = self .get_signed ()
20262017
2027- tmp = m .get_tmp ()
20282018 data = m .Reg (self .name ('data' ), width , initval = 0 , signed = signed )
20292019 valid = self .parent_value .sig_valid
20302020 ready = self .parent_value .sig_ready
@@ -2371,7 +2361,6 @@ def _implement(self, m, seq):
23712361 if not self .ops and self .size is not None :
23722362 width = 1
23732363
2374- tmp = m .get_tmp ()
23752364 data = m .Reg (self .name ('data' ), width ,
23762365 initval = initval_data , signed = signed )
23772366 valid = m .Reg (self .name ('valid' ), initval = 0 )
@@ -2833,7 +2822,6 @@ def read_multi(m, *vars, **opts):
28332822 if not vars :
28342823 raise ValueError ('No variables.' )
28352824
2836- tmp = m .get_tmp ()
28372825 all_valid = m .Wire (self .name ('_tmp_all_valid_' ))
28382826 all_valid_list = []
28392827 rdata_list = []
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