Skip to content

Commit 24905c8

Browse files
committed
README
1 parent 31b7ce3 commit 24905c8

File tree

3 files changed

+74
-3
lines changed

3 files changed

+74
-3
lines changed

README.md

Lines changed: 34 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ Run the script.
190190
python hello_led.py
191191
```
192192

193-
You will have a complete Verilog HDL source code named 'tmp.v' in the root directory, which is generated by the source code generator.
193+
You will have a complete Verilog HDL source code named 'tmp.v' as below, which is generated by the source code generator.
194194

195195
```verilog
196196
module test #
@@ -293,6 +293,39 @@ module blinkled #
293293
endmodule
294294
```
295295

296+
You will also see the simulation result of the generated Verilog code on Icarus Verilog.
297+
298+
```
299+
VCD info: dumpfile uut.vcd opened for output.
300+
LED: x count: x
301+
LED: x count: x
302+
LED: x count: x
303+
LED: x count: x
304+
LED: x count: x
305+
LED: x count: x
306+
LED: x count: x
307+
LED: x count: x
308+
LED: x count: x
309+
LED: x count: x
310+
LED: 0 count: 0
311+
LED: 0 count: 1
312+
LED: 0 count: 2
313+
LED: 0 count: 3
314+
LED: 0 count: 4
315+
...
316+
LED: 9 count: 777
317+
LED: 9 count: 778
318+
LED: 9 count: 779
319+
LED: 9 count: 780
320+
LED: 9 count: 781
321+
LED: 9 count: 782
322+
LED: 9 count: 783
323+
```
324+
325+
If you installed GTKwave and enable 'sim.view_waveform()' in 'hello_led.py', you can see the waveform the simulation result.
326+
327+
![waveform.png](img/waveform.png)
328+
296329

297330
Publication
298331
==============================

README.rst

Lines changed: 40 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -207,8 +207,8 @@ Run the script.
207207

208208
python hello_led.py
209209

210-
You will have a complete Verilog HDL source code named 'tmp.v' in the
211-
root directory, which is generated by the source code generator.
210+
You will have a complete Verilog HDL source code named 'tmp.v' as below,
211+
which is generated by the source code generator.
212212

213213
.. code:: verilog
214214
@@ -311,6 +311,44 @@ root directory, which is generated by the source code generator.
311311
312312
endmodule
313313
314+
You will also see the simulation result of the generated Verilog code on
315+
Icarus Verilog.
316+
317+
::
318+
319+
VCD info: dumpfile uut.vcd opened for output.
320+
LED: x count: x
321+
LED: x count: x
322+
LED: x count: x
323+
LED: x count: x
324+
LED: x count: x
325+
LED: x count: x
326+
LED: x count: x
327+
LED: x count: x
328+
LED: x count: x
329+
LED: x count: x
330+
LED: 0 count: 0
331+
LED: 0 count: 1
332+
LED: 0 count: 2
333+
LED: 0 count: 3
334+
LED: 0 count: 4
335+
...
336+
LED: 9 count: 777
337+
LED: 9 count: 778
338+
LED: 9 count: 779
339+
LED: 9 count: 780
340+
LED: 9 count: 781
341+
LED: 9 count: 782
342+
LED: 9 count: 783
343+
344+
If you installed GTKwave and enable 'sim.view\_waveform()' in
345+
'hello\_led.py', you can see the waveform the simulation result.
346+
347+
.. figure:: img/waveform.png
348+
:alt: waveform.png
349+
350+
waveform.png
351+
314352
Publication
315353
===========
316354

img/waveform.png

104 KB
Loading

0 commit comments

Comments
 (0)