New example of FSM

Author: shtaxxx

sample/fsm/Makefile

@@ -0,0 +1,39 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd
+
+.PHONY: sim
+sim:
+	iverilog -Wall tmp.v
+	./a.out
+
+.PHONY: view
+view:
+	gtkwave --giga uut.vcd &

sample/fsm/led.py

@@ -0,0 +1,69 @@
+import sys
+import os
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    valid = m.OutputReg('valid', initval=0)
+    
+    count = m.Reg('count', width=32, initval=0)
+    fsm = lib.FSM(m, 'fsm')
+    
+    for i in range(4):
+        fsm.goto_next()
+
+    # assert valid, then de-assert at the next cycle
+    fsm.add( valid(1) )
+    fsm.add( valid(0), delay=1 )
+    
+    for i in range(4):
+        fsm.goto_next()
+
+    # condition alias
+    c = (count >= 16)
+
+    # assert valid 1 cycle later if the condition is satisfied now
+    # then de-assert 3 cycles later with same condition
+    for i in range(4):
+        fsm.add( valid(1), cond=c, delay=1, keep=2)
+        fsm.add( valid(0), cond=c, delay=3 )
+        fsm.goto_next(cond=c)
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            m.reset(),
+        ).Else(
+            count(count + 1),
+            fsm.to_case()
+        ))
+
+    return m
+
+def mkTest():
+    m = Module('test')
+    clk = m.Reg('CLK')
+    rst = m.Reg('RST')
+    valid = m.Wire('valid')
+
+    uut = m.Instance(mkLed(), 'uut',
+                     #ports=(('CLK', clk), ('RST', rst), ('valid', valid)))
+                     ports=connect_same_name(clk, rst, valid))
+
+    lib.simulation.setup_waveform(m, uut)
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, period=100)
+
+    init.add(
+        Delay(1000),
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)